74LS00
SN74LS00N / DM74LS00NQuad 2-input NAND gate — the most common glue-logic part in retro computers.
Colour-coded DIP and PLCC diagrams, pin-by-pin detail, datasheet links and Machine Hub cross-references for 74 retro CPUs, custom video/sound chips, DRAM/SRAM and logic ICs
Colour-coded DIP and PLCC diagrams, pin-by-pin detail, datasheet links, and bi-directional Machine Hub cross-references for 76 classic CPUs, custom video/sound chips, DRAM/SRAM memories, and 74/4000-series logic ICs.
Quad 2-input NAND gate — the most common glue-logic part in retro computers.
Quad 2-input NOR gate — outputs on pins 1, 4, 10 and 13, the opposite pin order from the 74LS00.
Hex inverter — six independent NOT gates in one 14-pin DIP, the standard logic-level converter of the 74-series family.
Quad 2-input AND gate — same 14-pin pinout as the 74LS00, with outputs high only when both inputs are high.
3-to-8 line decoder with three enable inputs and eight active-low outputs — the classic memory-address decoder.
Dual 2-to-4 line decoder — two independent decoders, each with one active-low enable and four active-low outputs.
Hex Schmitt-trigger inverter — six NOT gates with hysteresis, the standard cure for slow or noisy input edges.
Octal 3-state buffer/line driver — two 4-bit groups with separate active-low enables, interleaved down the package.
Octal bidirectional 3-state bus transceiver — one direction pin and one active-low enable, the standard bidirectional bus driver.
Quad 2-input OR gate — same 14-pin pinout as the 74LS00, with outputs high when either input is high.
Octal transparent latch with 3-state outputs — level-sensitive latch enable on pin 11, the standard address latch for multiplexed buses.
Octal edge-triggered D flip-flop with 3-state outputs — rising-edge clock on pin 11, the standard registered bus driver.
Dual D flip-flop with asynchronous preset and clear (both active low) — the standard edge-triggered latch and divider of the 74-series.
Quad 2-input XOR gate — same 14-pin pinout as the 74LS00, with outputs high when the inputs differ.
Quad 2-input NOR gate — CMOS 4000-series part with the CD4011 pinout, NOT pin-compatible with the 74LS02 despite the same function.
Quad 2-input NAND gate — the CMOS 4000-series part, NOT pin-compatible with the 74LS00 despite the same function.
Dual D flip-flop with active-HIGH set and reset — CMOS counterpart to the 74LS74, but the preset/clear polarity is inverted.
Johnson decade counter with 10 decoded outputs — Q0-Q9 scattered around the package, not in pin order.
12-stage ripple-carry binary counter — Q1-Q12 outputs scrambled around the package, negative-edge clock.
Hex inverter/buffer — VDD on pin 1 and VSS on pin 8, the opposite end from every other part in this library; two NC pins.
Quad bilateral switch — four analogue/digital switches with independent controls; control pins are not adjacent to the switches they operate.
Quad 2-input NAND gate with Schmitt-trigger inputs — CMOS, follows the CD4011 pinout, the cure for slow or noisy input edges.
The original 8-bit microprocessor — three supply rails, a two-phase 12 V clock, and a repair hazard in the power sequencing.
The 8080 done properly — one +5 V rail, an on-chip clock oscillator, and a multiplexed address/data bus latched by ALE.
The 8-bit CPU at the heart of the Apple II, PET, VIC-20, BBC Micro and Atari 2600.
The Commodore 64 CPU — a 6502 core with a 6-bit I/O port and AEC bus-acknowledge pin.
The Commodore 16 and Plus/4 CPU — a 6502 core with a 7-bit I/O port, no /NMI and no PHI2 output.
The Commodore 128 CPU — a 6510 with a 7-bit I/O port, running at 1 MHz or 2 MHz.
16/32-bit CPU at the heart of the Amiga, Atari ST, original Macintosh and Sega Mega Drive.
Full 32-bit 68000 internal architecture with an 8-bit external data bus and 1 MB (20-bit) address space — the heart of the Sinclair QL.
The first single-chip 16-bit microprocessor — three supply rails (-5V, +5V, +12V), a four-phase 12V clock, and reversed big-endian bit numbering.
The most capable 8-bit CPU of its generation — position-independent code, hardware multiply, and a clean contiguous bus.
The CMOS 6502 people actually buy today — fully static, runs to 14 MHz, but NOT a drop-in for the NMOS 6502 without pin 1, 5 and 36 attention.
The 8-bit CPU behind the ZX Spectrum, MSX, Amstrad CPC and countless CP/M machines.
Three 16-bit timers, six modes — and the three counters pins appear in three different orders, the signature trap.
Three 8-bit I/O ports in one 40-pin DIP — port C nibbles run in opposite directions and RESET is active high, the two signature traps.
Two 8-bit I/O ports, two 16-bit timers and a shift register — the 6502 family peripheral chip.
Two 8-bit I/O ports, two timers, a time-of-day clock and a serial port — the C64 peripheral chip.
Two 8-bit I/O ports with two interrupt lines each — the 6800-family peripheral chip, half-shared with the 6522 and 6526.
Serial UART for the 6800 family — split TX/RX clocks, three mixed-polarity chip selects, and both power pins on the left-hand side.
The C64 PLA — 16 inputs, 8 outputs, 48 product terms. The most failure-prone part in a Commodore 64.
The Commodore 128's Memory Management Unit — switches between Z80, C128 (8502) and C64 modes, banks 128KB RAM, and relocates Zero-Page and Stack.
The 16-pin master clock multiplier/divider in the Commodore 64 (ASSY 250425/250466) and Commodore 128 — generates Color Clock and Dot Clock from a single crystal.
The Synchronous Address Multiplexer of the Dragon 32/64 and CoCo 1/2 — generates E/Q CPU clocks, interleaved VDG/CPU DRAM cycles, and S0-S2 device chip selects.
The compact 28-pin single-rail (+5V) FM/MFM floppy controller with built-in digital data separator and motor-on timer — used in the Atari ST, BBC Micro/Master and C128D/1571/1581.
The industry-standard multi-sector FM/MFM floppy controller behind the Amstrad CPC 664/6128, ZX Spectrum +3, Kaypro, and IBM PC/XT/AT.
Three square-wave channels, a noise generator and an envelope generator — the sound chip of the MSX, Spectrum 128 and countless arcades.
The VIC-20 video and sound chip — display, three tone oscillators, noise and paddle ADC in one part.
The Commodore 64 video chip — generates the display, the system clock and the DRAM timing.
The Commodore 64's sound chip — three-voice synthesiser with filter, envelope and paddle ADC.
The later C64/C128 sound chip — same pinout as the 6581 but 9 V supply and a cleaner filter.
The CRT controller behind the Amstrad CPC, BBC Micro, IBM MDA and CGA — two opposing address buses and one register-select pin.
TI's write-only sound chip — D0 is the MOST significant bit, opposite to every other chip in this library. Read the data bus warning.
The VDP behind the MSX, ColecoVision and TI-99/4A — every bus is numbered backwards: CD0, AD0 and RD0 are the MOST significant bits.
Yamaha's licensed AY-3-8910 — pin compatible with one pin difference (SEL on pin 26) and a 5-bit envelope counter.
The Commodore 128's 80-column RGBI Video Display Controller — accessed through just two I/O registers ($D600/$D601) with its own private 16KB or 64KB VRAM.
The single-chip heart of the Commodore 16, C116 and Plus/4 — 121-colour video, 2-channel sound, 3 timers, DRAM refresh and unbuffered joystick/keyboard latch.
The Video Display Generator behind the Dragon 32/64, Tandy Color Computer 1/2, Acorn Atom and Mattel Aquarius — outputs native Y, R-Y and B-Y component video.
The custom Gate Array of the Amstrad CPC 464, 664 and 6128 — generates the 4 MHz Z80 clock, 1 MHz 6845 CRTC clock, 27-colour RGB palette, and ROM banking.
The Ferranti Uncommitted Logic Array of the ZX Spectrum 16K/48K/Plus — drives the 16KB 4116 lower RAM, Y/U/V PAL video, keyboard matrix, EAR/MIC tape and beeper.
Atari's programmable Display List processor — fetches its own Display List programs via 6502 /HALT DMA, generates Display List Interrupts (DLIs), and streams AN0-AN2 pixel data to GTIA.
Atari's Graphics Television Interface Adaptor — converts ANTIC AN0-AN2 streams into 256 colours (LUM0-3 + COLOR), renders 4 Players & 4 Missiles, and reads START/SELECT/OPTION.
Atari's Potentiometer and Keyboard Integrated Circuit — 4-channel audio synthesizer, 64-key scanner, 8 paddle ADCs, hardware PRNG, and high-speed SIO serial UART.
The central DMA, Blitter, Copper and Chip RAM controller of the Amiga 500, 2000 and 3000 — 25 DMA channels, RGA register bus, and 512KB/1MB/2MB Chip RAM addressing.
The Amiga's Display Encoder — renders 6-bitplane HAM/EHB playfields, 8 hardware sprites, 12-bit (4096-colour) RGB output, and quadrature mouse counters.
The unchanged sonic heart of every Amiga from the 1985 A1000 to the 1992 A4000 — 4-channel 8-bit DMA audio, MFM floppy controller, interrupt controller, UART, and proportional pots.
Texas Instruments' Linear Predictive Coding (LPC-10) vocal tract synthesizer — used in the TI-99/4A Speech Synthesizer, Acorn BBC Micro, Apple II Echo II and arcade classics.
1024 x 4 static RAM — data pins numbered from ONE (DQ1-DQ4, no DQ0), used in pairs for byte-wide storage.
8K x 8 UV-erasable EPROM, the JEDEC 28-pin byte-wide standard. Same pinout as the 6264 SRAM except for four pins.
16K x 1 DRAM with FOUR supply pins and THREE rails. A 4164 fitted here receives +12 V on its 5 V pin and will not survive.
64K x 1 DRAM, single +5 V. VCC is pin 8 and GND is pin 16 — the reverse of almost every other 16-pin DIP. Apply 5 V to pin 16 and it dies.
The 18-pin nibble-wide (x4) DRAM family — just TWO chips replace eight 4116/4164 DRAMs! Upgrading 4416 to 4464 unlocks 64KB on the C16, C128 VDC, CoCo 2 and Atari 600XL.
8K x 8 SRAM, the JEDEC 28-pin byte-wide standard. Two chip selects of opposite polarity — leave CS2 floating and it never responds.
Dual op-amp, single-supply. The two halves are MIRRORED — inputs swap round between them. Output cannot swing all the way to V+.
Dual RS-232 driver/receiver — generates +/-10 V from a single +5 V rail. Six of sixteen pins carry no signal (charge pump and caps).
The classic 555 timer — astable, monostable and bistable modes from a single 8-pin chip.
A pinout is only useful if you can hold the chip the right way round and tell a power pin from a signal pin. The diagrams above follow the convention every datasheet uses, and the colour groups are there so you can spot the supply and bus pins at a glance before you reach for a probe.
On a DIP package, pin 1 is marked in two ways that should agree: a small dot moulded into the top of the case next to pin 1, and a semicircular notch cut into the top edge. Hold the chip with the notch uppermost and pin 1 is on your left; numbering then runs anticlockwise, down the left side and back up the right. On a square J-leaded PLCC package (such as the 84-pin Amiga Fat Agnus), a chamfered top-left corner and a small dimple in the middle of the top edge mark pin 1 at the top-centre; numbering runs anticlockwise around all four sides.
Every pin is coloured by its function so the supply and bus structure stands out. Red is power, grey is ground, amber is a clock or timing pin, blue is the address bus, green the data bus, purple a control line, cyan general I/O, pink an analogue pin, and a muted grey marks a no-connect. The legend above the diagram lets you isolate one group at a time — useful on a 48-, 64-, or 84-pin part where the address and data buses otherwise dominate the picture.
The address, data and control pins are coloured as groups rather than individually because on a CPU they behave as groups: the address bus drives memory together, the data bus reads and writes together, and the control strobes fire in a fixed sequence. When a board faults, it is rarely one pin — a stuck address line usually means a shorted decoder or a dead buffer upstream, and a floating data bit often points to a failed transceiver, not the CPU. Grouping the colours makes those patterns visible.
Before lifting a chip, probe it in circuit. Check the supply pins first — a gate with no VCC or a CPU with a missing clock will look dead and is usually not the chip's fault. On logic, drive an input and watch the output; a totem-pole output that never pulls low or high has a failed transistor, and an open-collector pin that stays high regardless of its input has lost its pull-up. On a CPU, scope the clock and the reset line, then the address bus during a reset fetch; a bus that never toggles points to a stuck peripheral holding the line, which is far more common than a dead CPU. Only when the supplies, clock and bus activity all look correct is the chip itself the prime suspect.
Every chip in this library is cross-linked to the dedicated Machine Hubs where it appears on the bench:
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