74LS00
SN74LS00N / DM74LS00NQuad 2-input NAND gate — the most common glue-logic part in retro computers.
Colour-coded DIP and PLCC diagrams, pin-by-pin detail and datasheet links for retro logic, CPUs and support chips
Colour-coded DIP and PLCC diagrams, pin-by-pin detail and datasheet links for retro logic, CPUs and support chips. Search the library, filter by family, or click any pin in the live diagram for its signal, direction and voltage.
Quad 2-input NAND gate — the most common glue-logic part in retro computers.
Quad 2-input NOR gate — outputs on pins 1, 4, 10 and 13, the opposite pin order from the 74LS00.
Hex inverter — six independent NOT gates in one 14-pin DIP, the standard logic-level converter of the 74-series family.
Quad 2-input AND gate — same 14-pin pinout as the 74LS00, with outputs high only when both inputs are high.
3-to-8 line decoder with three enable inputs and eight active-low outputs — the classic memory-address decoder.
Dual 2-to-4 line decoder — two independent decoders, each with one active-low enable and four active-low outputs.
Hex Schmitt-trigger inverter — six NOT gates with hysteresis, the standard cure for slow or noisy input edges.
Octal 3-state buffer/line driver — two 4-bit groups with separate active-low enables, interleaved down the package.
Octal bidirectional 3-state bus transceiver — one direction pin and one active-low enable, the standard bidirectional bus driver.
Quad 2-input OR gate — same 14-pin pinout as the 74LS00, with outputs high when either input is high.
Octal transparent latch with 3-state outputs — level-sensitive latch enable on pin 11, the standard address latch for multiplexed buses.
Octal edge-triggered D flip-flop with 3-state outputs — rising-edge clock on pin 11, the standard registered bus driver.
Dual D flip-flop with asynchronous preset and clear (both active low) — the standard edge-triggered latch and divider of the 74-series.
Quad 2-input XOR gate — same 14-pin pinout as the 74LS00, with outputs high when the inputs differ.
Quad 2-input NOR gate — CMOS 4000-series part with the CD4011 pinout, NOT pin-compatible with the 74LS02 despite the same function.
Quad 2-input NAND gate — the CMOS 4000-series part, NOT pin-compatible with the 74LS00 despite the same function.
Dual D flip-flop with active-HIGH set and reset — CMOS counterpart to the 74LS74, but the preset/clear polarity is inverted.
Johnson decade counter with 10 decoded outputs — Q0-Q9 scattered around the package, not in pin order.
12-stage ripple-carry binary counter — Q1-Q12 outputs scrambled around the package, negative-edge clock.
Hex inverter/buffer — VDD on pin 1 and VSS on pin 8, the opposite end from every other part in this library; two NC pins.
Quad bilateral switch — four analogue/digital switches with independent controls; control pins are not adjacent to the switches they operate.
Quad 2-input NAND gate with Schmitt-trigger inputs — CMOS, follows the CD4011 pinout, the cure for slow or noisy input edges.
16/32-bit CPU at the heart of the Amiga, Atari ST, original Macintosh and Sega Mega Drive.
The 8-bit CPU behind the ZX Spectrum, MSX, Amstrad CPC and countless CP/M machines.
The Commodore 64's sound chip — three-voice synthesiser with filter, envelope and paddle ADC.
The classic 555 timer — astable, monostable and bistable modes from a single 8-pin chip.
A pinout is only useful if you can hold the chip the right way round and tell a power pin from a signal pin. The diagrams above follow the convention every datasheet uses, and the colour groups are there so you can spot the supply and bus pins at a glance before you reach for a probe.
On a DIP package, pin 1 is marked in two ways that should agree: a small dot moulded into the top of the case next to pin 1, and a semicircular notch cut into the top edge. Hold the chip with the notch uppermost and pin 1 is on your left; numbering then runs anticlockwise, down the left side and back up the right. If the dot and the notch disagree, trust the notch — a re-marked or counterfeit part can have a stray dot, but the notch is part of the moulding. The diagrams here draw the notch on the top edge and pin 1 at the top-left, exactly as you would hold the real part.
Every pin is coloured by its function so the supply and bus structure stands out. Red is power, grey is ground, amber is a clock or timing pin, blue is the address bus, green the data bus, purple a control line, cyan general I/O, pink an analogue pin, and a muted grey marks a no-connect. The legend above the diagram lets you isolate one group at a time — useful on a 64-pin part where the address and data buses otherwise dominate the picture.
The address, data and control pins are coloured as groups rather than individually because on a CPU they behave as groups: the address bus drives memory together, the data bus reads and writes together, and the control strobes fire in a fixed sequence. When a board faults, it is rarely one pin — a stuck address line usually means a shorted decoder or a dead buffer upstream, and a floating data bit often points to a failed transceiver, not the CPU. Grouping the colours makes those patterns visible.
Before lifting a chip, probe it in circuit. Check the supply pins first — a gate with no VCC or a CPU with a missing clock will look dead and is usually not the chip's fault. On logic, drive an input and watch the output; a totem-pole output that never pulls low or high has a failed transistor, and an open-collector pin that stays high regardless of its input has lost its pull-up. On a CPU, scope the clock and the reset line, then the address bus during a reset fetch; a bus that never toggles points to a stuck peripheral holding the line, which is far more common than a dead CPU. Only when the supplies, clock and bus activity all look correct is the chip itself the prime suspect.