Interactive IC Pinout & Datasheet Quick-Finder

Colour-coded DIP and PLCC diagrams, pin-by-pin detail and datasheet links for retro logic, CPUs and support chips

Interactive IC Pinout & Datasheet Quick-Finder

Colour-coded DIP and PLCC diagrams, pin-by-pin detail and datasheet links for retro logic, CPUs and support chips. Search the library, filter by family, or click any pin in the live diagram for its signal, direction and voltage.

74-Series Logic DIP-14

74LS00

SN74LS00N / DM74LS00N

Quad 2-input NAND gate — the most common glue-logic part in retro computers.

74-Series Logic DIP-14

74LS02

SN74LS02N / DM74LS02N

Quad 2-input NOR gate — outputs on pins 1, 4, 10 and 13, the opposite pin order from the 74LS00.

74-Series Logic DIP-14

74LS04

SN74LS04N / DM74LS04N

Hex inverter — six independent NOT gates in one 14-pin DIP, the standard logic-level converter of the 74-series family.

74-Series Logic DIP-14

74LS08

SN74LS08N / DM74LS08N

Quad 2-input AND gate — same 14-pin pinout as the 74LS00, with outputs high only when both inputs are high.

74-Series Logic DIP-16

74LS138

SN74LS138N / DM74LS138

3-to-8 line decoder with three enable inputs and eight active-low outputs — the classic memory-address decoder.

74-Series Logic DIP-16

74LS139

SN74LS139N / DM74LS139A

Dual 2-to-4 line decoder — two independent decoders, each with one active-low enable and four active-low outputs.

74-Series Logic DIP-14

74LS14

SN74LS14N / DM74LS14N

Hex Schmitt-trigger inverter — six NOT gates with hysteresis, the standard cure for slow or noisy input edges.

74-Series Logic DIP-20

74LS244

SN74LS244N / DM74LS244

Octal 3-state buffer/line driver — two 4-bit groups with separate active-low enables, interleaved down the package.

74-Series Logic DIP-20

74LS245

SN74LS245N / DM74LS245

Octal bidirectional 3-state bus transceiver — one direction pin and one active-low enable, the standard bidirectional bus driver.

74-Series Logic DIP-14

74LS32

SN74LS32N / DM74LS32N

Quad 2-input OR gate — same 14-pin pinout as the 74LS00, with outputs high when either input is high.

74-Series Logic DIP-20

74LS373

SN74LS373N / DM74LS373

Octal transparent latch with 3-state outputs — level-sensitive latch enable on pin 11, the standard address latch for multiplexed buses.

74-Series Logic DIP-20

74LS374

SN74LS374N / DM74LS374

Octal edge-triggered D flip-flop with 3-state outputs — rising-edge clock on pin 11, the standard registered bus driver.

74-Series Logic DIP-14

74LS74

SN74LS74AN / DM74LS74A

Dual D flip-flop with asynchronous preset and clear (both active low) — the standard edge-triggered latch and divider of the 74-series.

74-Series Logic DIP-14

74LS86

SN74LS86AN / DM74LS86A

Quad 2-input XOR gate — same 14-pin pinout as the 74LS00, with outputs high when the inputs differ.

4000-Series CMOS DIP-14

CD4001

CD4001BC / MC14001 / HEF4001

Quad 2-input NOR gate — CMOS 4000-series part with the CD4011 pinout, NOT pin-compatible with the 74LS02 despite the same function.

4000-Series CMOS DIP-14

CD4011

CD4011BC / MC14011 / HEF4011

Quad 2-input NAND gate — the CMOS 4000-series part, NOT pin-compatible with the 74LS00 despite the same function.

4000-Series CMOS DIP-14

CD4013

CD4013BC / MC14013 / HEF4013

Dual D flip-flop with active-HIGH set and reset — CMOS counterpart to the 74LS74, but the preset/clear polarity is inverted.

4000-Series CMOS DIP-16

CD4017

CD4017BC / MC14017 / HEF4017

Johnson decade counter with 10 decoded outputs — Q0-Q9 scattered around the package, not in pin order.

4000-Series CMOS DIP-16

CD4040

CD4040BC / MC14040 / HEF4040

12-stage ripple-carry binary counter — Q1-Q12 outputs scrambled around the package, negative-edge clock.

4000-Series CMOS DIP-16

CD4049

CD4049UB / MC14049 / HEF4049

Hex inverter/buffer — VDD on pin 1 and VSS on pin 8, the opposite end from every other part in this library; two NC pins.

4000-Series CMOS DIP-14

CD4066

CD4066B / MC14066 / HEF4066

Quad bilateral switch — four analogue/digital switches with independent controls; control pins are not adjacent to the switches they operate.

4000-Series CMOS DIP-14

CD4093

CD4093B / MC14093 / HEF4093

Quad 2-input NAND gate with Schmitt-trigger inputs — CMOS, follows the CD4011 pinout, the cure for slow or noisy input edges.

CPUs & MPUs DIP-64

Motorola 68000

MC68000 / MC68HC000

16/32-bit CPU at the heart of the Amiga, Atari ST, original Macintosh and Sega Mega Drive.

CPUs & MPUs DIP-40

Zilog Z80

Z8400 / Z84C00

The 8-bit CPU behind the ZX Spectrum, MSX, Amstrad CPC and countless CP/M machines.

Sound & Video DIP-28

MOS 6581 SID

MOS 6581 / 6581R4

The Commodore 64's sound chip — three-voice synthesiser with filter, envelope and paddle ADC.

Analog & Interface DIP-8

NE555

NE555 / LM555 / SA555

The classic 555 timer — astable, monostable and bistable modes from a single 8-pin chip.

How to Read These Pinouts

A pinout is only useful if you can hold the chip the right way round and tell a power pin from a signal pin. The diagrams above follow the convention every datasheet uses, and the colour groups are there so you can spot the supply and bus pins at a glance before you reach for a probe.

Orienting a DIP

On a DIP package, pin 1 is marked in two ways that should agree: a small dot moulded into the top of the case next to pin 1, and a semicircular notch cut into the top edge. Hold the chip with the notch uppermost and pin 1 is on your left; numbering then runs anticlockwise, down the left side and back up the right. If the dot and the notch disagree, trust the notch — a re-marked or counterfeit part can have a stray dot, but the notch is part of the moulding. The diagrams here draw the notch on the top edge and pin 1 at the top-left, exactly as you would hold the real part.

What the colours mean

Every pin is coloured by its function so the supply and bus structure stands out. Red is power, grey is ground, amber is a clock or timing pin, blue is the address bus, green the data bus, purple a control line, cyan general I/O, pink an analogue pin, and a muted grey marks a no-connect. The legend above the diagram lets you isolate one group at a time — useful on a 64-pin part where the address and data buses otherwise dominate the picture.

Why bus pins are grouped

The address, data and control pins are coloured as groups rather than individually because on a CPU they behave as groups: the address bus drives memory together, the data bus reads and writes together, and the control strobes fire in a fixed sequence. When a board faults, it is rarely one pin — a stuck address line usually means a shorted decoder or a dead buffer upstream, and a floating data bit often points to a failed transceiver, not the CPU. Grouping the colours makes those patterns visible.

Testing suspect logic in circuit

Before lifting a chip, probe it in circuit. Check the supply pins first — a gate with no VCC or a CPU with a missing clock will look dead and is usually not the chip's fault. On logic, drive an input and watch the output; a totem-pole output that never pulls low or high has a failed transistor, and an open-collector pin that stays high regardless of its input has lost its pull-up. On a CPU, scope the clock and the reset line, then the address bus during a reset fetch; a bus that never toggles points to a stuck peripheral holding the line, which is far more common than a dead CPU. Only when the supplies, clock and bus activity all look correct is the chip itself the prime suspect.

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