Pinout diagram
Used in Retro Machine Hubs
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Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description | Expected Signal |
|---|---|---|---|---|---|---|
| 1 | /1G (Strobe 1) | Control | Input | TTL, active low | Active-low enable strobe for Multiplexer 1. Tied to GND (0 V) in the Amstrad CPC 464. | |
| 2 | B (Select MSB) | Control | Input | TTL | Common binary select input B (MSB). In the CPC 464, driven by Gate Array Pin 21 (/CPU) to switch between CPU and CRTC video cycles. | |
| 3 | 1C3 | Address Bus | Input | TTL | Multiplexer 1 Data Input 3 (selected when B=1, A=1). | |
| 4 | 1C2 | Address Bus | Input | TTL | Multiplexer 1 Data Input 2 (selected when B=1, A=0). | |
| 5 | 1C1 | Address Bus | Input | TTL | Multiplexer 1 Data Input 1 (selected when B=0, A=1). | |
| 6 | 1C0 | Address Bus | Input | TTL | Multiplexer 1 Data Input 0 (selected when B=0, A=0). | |
| 7 | 1Y (Output 1) | Address Bus | Output | TTL | Multiplexer 1 Non-Inverting Output (feeds one of the 4164 DRAM address lines A0–A7). | |
| 8 | GND | Ground | Power | 0 V | 0 V System Ground. | |
| 9 | 2Y (Output 2) | Address Bus | Output | TTL | Multiplexer 2 Non-Inverting Output (feeds one of the 4164 DRAM address lines A0–A7). | |
| 10 | 2C0 | Address Bus | Input | TTL | Multiplexer 2 Data Input 0 (selected when B=0, A=0). | |
| 11 | 2C1 | Address Bus | Input | TTL | Multiplexer 2 Data Input 1 (selected when B=0, A=1). | |
| 12 | 2C2 | Address Bus | Input | TTL | Multiplexer 2 Data Input 2 (selected when B=1, A=0). | |
| 13 | 2C3 | Address Bus | Input | TTL | Multiplexer 2 Data Input 3 (selected when B=1, A=1). | |
| 14 | A (Select LSB) | Control | Input | TTL | Common binary select input A (LSB). In the CPC 464, driven by Gate Array Pin 17 (/CASAD) to switch between Row (/RAS) and Column (/CAS) addresses. | |
| 15 | /2G (Strobe 2) | Control | Input | TTL, active low | Active-low enable strobe for Multiplexer 2. Tied to GND (0 V) in the Amstrad CPC 464. | |
| 16 | VCC (+5V) | Power | Power | +5.0 V DC | +5.0 V DC positive supply. |
Common uses and repair diagnostics
The 74LS153 contains two independent 4-line-to-1-line data multiplexers inside a 16-pin DIP package, controlled by two common binary select inputs (Select B on Pin 2, Select A on Pin 14) and two separate active-low enable strobes (/1G on Pin 1, /2G on Pin 15). In the Amstrad CPC 464 (IC109 and IC110 on Type 1 Long-Boards; IC107 and IC108 on some short-boards), four 74LS153s (or two 74LS153s paired with 74LS157s) perform the critical job of switching the 8-bit multiplexed address bus of the eight 4164 DRAMs between four sources: Z80 CPU Row Address, Z80 CPU Column Address, 6845 CRTC Video Row Address (MA/RA), and 6845 CRTC Video Column Address — driven by the Gate Array's /CPU (Pin 21) and /CASAD (Pin 17) signals!
In the Amstrad CPC 464, 664, and 6128 (and Commodore 64/Plus/4 equivalences using 74LS257/74LS157), the 74LS153 multiplexes the Z80 CPU's 16-bit address bus and the 6845 CRTC's 14-bit MA + 3-bit RA video address bus onto the 8-pin address bus of the 4164 DRAM bank.
Diagnostic signature on an Amstrad CPC 464: Unlike a single bad 4164 DRAM chip (which corrupts only ONE data bit across every byte), a faulty 74LS153 (IC109 or IC110) corrupts an entire DRAM address line — causing duplicated character rows on screen, mirrored screen bands, or a solid yellow/blue screen where the Z80 crashes immediately upon stack push/pop even when all eight 4164 RAM chips test 100% healthy!
- Scope Pin 2 (Select B = /CPU from Gate Array Pin 21) and Pin 14 (Select A = /CASAD from Gate Array Pin 17) for continuous MHz switching activity.
- Scope Outputs 1Y (Pin 7) and 2Y (Pin 9): both must show clean 0 V to 4 V TTL square transitions. A stuck-high, stuck-low, or 1.5 V mid-level output on Pin 7 or Pin 9 causes instant RAM addressing failure across all eight 4164 chips.
- Verify Strobes /1G (Pin 1) and /2G (Pin 15) are held low (0 V).