Pinout diagram
Used in Retro Machine Hubs
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Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | VSS | Ground | Power | 0 V | System ground (0 V). |
| 2 | A3 | Address Bus | Bidirectional | TTL | Address bit 3 (input during CPU register writes to $D40x; output during ANTIC DMA & refresh!). |
| 3 | A2 | Address Bus | Bidirectional | TTL | Address bit 2 (bidirectional). |
| 4 | A1 | Address Bus | Bidirectional | TTL | Address bit 1 (bidirectional). |
| 5 | A0 | Address Bus | Bidirectional | TTL | Address bit 0 (bidirectional). |
| 6 | A4 | Address Bus | Output | TTL | Address bit 4 (driven by ANTIC during DMA/refresh). |
| 7 | A5 | Address Bus | Output | TTL | Address bit 5. |
| 8 | /REF | Control | Output | TTL, active low | DRAM Refresh cycle indicator (9 refresh cycles per scanline). |
| 9 | /HALT | Control | Output | TTL, active low | CPU Halt output (feeds SALLY 6502C Pin 35 so ANTIC can perform Display List and sprite DMA). |
| 10 | A6 | Address Bus | Output | TTL | Address bit 6. |
| 11 | R/W | Control | Input | TTL | Read/Write input from 6502C. |
| 12 | PHI2 | Clock / Timing | Output | TTL 1.79 MHz | Phase 2 clock output. |
| 13 | /RST | Control | Input | TTL, active low | System Reset input. |
| 14 | /NMI | Control | Output | TTL, active low | Non-Maskable Interrupt output to 6502C Pin 6 (fires Vertical Blank Interrupts and mid-screen Display List Interrupts!). |
| 15 | /CS | Control | Input | TTL, active low | Chip Select input ($D400-$D4FF from MMU/decoder). |
| 16 | D7 | Data Bus | Bidirectional | TTL | Data bus bit 7. |
| 17 | D6 | Data Bus | Bidirectional | TTL | Data bus bit 6. |
| 18 | D5 | Data Bus | Bidirectional | TTL | Data bus bit 5. |
| 19 | D4 | Data Bus | Bidirectional | TTL | Data bus bit 4. |
| 20 | D0 | Data Bus | Bidirectional | TTL | Data bus bit 0. |
| 21 | VCC | Power | Power | +5 V | +5 V main supply. |
| 22 | D1 | Data Bus | Bidirectional | TTL | Data bus bit 1. |
| 23 | D2 | Data Bus | Bidirectional | TTL | Data bus bit 2. |
| 24 | D3 | Data Bus | Bidirectional | TTL | Data bus bit 3. |
| 25 | A12 | Address Bus | Output | TTL | Address bit 12. |
| 26 | A13 | Address Bus | Output | TTL | Address bit 13. |
| 27 | A14 | Address Bus | Output | TTL | Address bit 14. |
| 28 | A15 | Address Bus | Output | TTL | Address bit 15. |
| 29 | PHI0 | Clock / Timing | Output | TTL 1.79 MHz | Master CPU clock output (feeds SALLY 6502C Pin 37!). If dead, the CPU gets no clock! |
| 30 | AN2 | I/O | Output | TTL | ANTIC-to-GTIA bus bit 2. |
| 31 | AN1 | I/O | Output | TTL | ANTIC-to-GTIA bus bit 1. |
| 32 | AN0 | I/O | Output | TTL | ANTIC-to-GTIA bus bit 0 (carries playfield pixels and HSYNC/VSYNC commands to GTIA). |
| 33 | RDY | Control | Output | Open-drain | CPU Ready output (pulled low when CPU writes to $D40A WSYNC to pause CPU until exact horizontal blank!). |
| 34 | FPHI0 | Clock / Timing | Input | TTL 3.58 MHz | Fast Phase 0 master dot clock input (3.5795 MHz NTSC / 3.5468 MHz PAL). |
| 35 | /LP | I/O | Input | TTL, active low | Light Pen strobe input (latches PENH/PENV counters). |
| 36 | /RAS | Control | Output | TTL, active low | Row Address Strobe output (on non-FREDDIE machines). |
| 37 | A11 | Address Bus | Output | TTL | Address bit 11. |
| 38 | A10 | Address Bus | Output | TTL | Address bit 10. |
| 39 | A9 | Address Bus | Output | TTL | Address bit 9. |
| 40 | A8 / A7 | Address Bus | Output | TTL | Address bit 7 / 8 output. |
Common uses and repair diagnostics
Designed by Jay Miner, Joe Decuir, and François Michel, the 40-pin Atari ANTIC (Alphanumeric Television Interface Controller) is a true dedicated microprocessor that executes its own screen program called a Display List! By asserting /HALT (Pin 9) to pause the SALLY 6502C CPU, ANTIC takes over the 16-bit address bus (A0-A15) to fetch Display List instructions, screen data, and Player-Missile (sprite) DMA directly from RAM, refreshes the DRAM (/REF on Pin 8), fires mid-screen Display List Interrupts (DLIs on Pin 14 /NMI), and streams a 3-bit encoded pixel/sync command bus (AN0-AN2, Pins 30-32) into the companion GTIA/CTIA chip.
Used in every Atari 8-bit computer (400, 800, 1200XL, 600XL, 800XL, 65XE, 130XE, XEGS) and the Atari 5200 SuperSystem. Remember: ANTIC determines whether an Atari runs at 60 Hz (NTSC CO12296/CO14887, 262 lines) or 50 Hz (PAL CO21697, 312 lines)!
- Scope Pin 29 (PHI0): ANTIC divides the 3.58 MHz clock on Pin 34 (FPHI0) by 2 to generate the 1.79 MHz CPU clock on Pin 29. If Pin 29 is dead, the SALLY 6502C cannot run!
- Scope Pins 30-32 (AN0-AN2): even if the CPU is halted on a solid red/brown screen, ANTIC still sends HSYNC/VSYNC codes to GTIA over AN0-AN2.