Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | Q5 | I/O | Output | CMOS push-pull | Decoded output 5. High when the counter is at count 5; low otherwise. |
| 2 | Q1 | I/O | Output | CMOS push-pull | Decoded output 1. High when the counter is at count 1; low otherwise. |
| 3 | Q0 | I/O | Output | CMOS push-pull | Decoded output 0. High when the counter is at count 0 (the reset state); low otherwise. |
| 4 | Q2 | I/O | Output | CMOS push-pull | Decoded output 2. High when the counter is at count 2; low otherwise. |
| 5 | Q6 | I/O | Output | CMOS push-pull | Decoded output 6. High when the counter is at count 6; low otherwise. |
| 6 | Q7 | I/O | Output | CMOS push-pull | Decoded output 7. High when the counter is at count 7; low otherwise. |
| 7 | Q3 | I/O | Output | CMOS push-pull | Decoded output 3. High when the counter is at count 3; low otherwise. |
| 8 | VSS | Ground | Power | 0 V | Ground return. |
| 9 | Q8 | I/O | Output | CMOS push-pull | Decoded output 8. High when the counter is at count 8; low otherwise. |
| 10 | Q4 | I/O | Output | CMOS push-pull | Decoded output 4. High when the counter is at count 4; low otherwise. |
| 11 | Q9 | I/O | Output | CMOS push-pull | Decoded output 9. High when the counter is at count 9; low otherwise. |
| 12 | CO | I/O | Output | CMOS push-pull, active high | Carry output, active HIGH. High for counts 0-4, low for counts 5-9. Used to chain two CD4017s into a divide-by-100: feed CO to the clock enable of the next stage. This is an active-high divide-by-ten output, NOT an active-low strobe. |
| 13 | /CE | Control | Input | CMOS, 0 V / VDD, active low | Clock enable, active low. When low, the counter advances on the rising clock edge; when high, the counter holds and the clock is ignored. Can also be used as a negative-edge clock input. |
| 14 | CLOCK | Clock / Timing | Input | CMOS, rising edge | Clock input, positive-edge triggered. The counter advances on the low-to-high transition when /CE is low. |
| 15 | RESET | Control | Input | CMOS, 0 V / VDD, active high | Master reset, active HIGH. Pulling this pin high forces the counter to count 0 (Q0 high, all others low). Must be held low for normal counting. |
| 16 | VDD | Power | Power | +3 V to +15 V | Positive supply. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The CD4017 is the 4000-series Johnson decade counter — a 5-stage Johnson counter that drives ten decoded outputs, one at a time, in sequence. On every rising clock edge the active output advances from Q0 to Q9 and then back to Q0. The decade outputs are scattered around the package in no obvious order — Q0 is on pin 3, Q1 on pin 2, Q2 on pin 4, and so on — so the pinout must be transcribed from the datasheet, not inferred from a pattern. The part also provides a carry output that goes low for the first five counts and high for the second five, which lets two CD4017s chain into a divide-by-100.
The CD4017 is the standard decade counter on boards that need to sequence through ten states — LED chasers, stepper motor drivers, divide-by-N counters, and one-of-ten selectors. The ten decoded outputs mean no external decoder is needed: each output drives one stage directly. The carry output lets two CD4017s chain into a divide-by-100, and the active-low clock enable lets the counter be gated by another signal without an extra gate. The Johnson counter design means the outputs are glitch-free — only one output is high at a time, and the transition between counts is clean, which is why the part is preferred over a binary counter plus decoder for display driving.
The trap with the CD4017 is the output pin order. Q0 is on pin 3, Q1 on pin 2, Q2 on pin 4, and the rest are scattered similarly. A board laid out assuming Q0 is on pin 1 will wire the wrong LED to the wrong count, so always verify against the datasheet.
- Confirm pin 16 (VDD) is within 3 to 15 V and pin 8 (VSS) is at 0 V. Overvoltage or reversed rails kill CMOS instantly.
- Hold /CE low and RESET low, then clock CLOCK: the outputs should advance Q0, Q1, Q2 ... Q9, Q0 in sequence. A skipped or extra step means a dead counter stage or a bouncing clock.
- Pull RESET high and check Q0 goes high and all other Q outputs go low. If RESET does not work, the pin is damaged or tied incorrectly.
- Check CO is high for counts 0-4 and low for counts 5-9. A stuck carry means the internal Johnson counter is miscounting.
- If the counter skips counts, scope the clock — a slow or bouncing edge can double-clock the counter. The /CE pin can also be used as a second clock input (negative edge) if CLOCK is held high.