Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | A10 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 10. The address bus has no pattern at all: A10 alone on pin 1, A0-A2 on 25-27, A3-A9 on 29-35, then A15 on 36, A12 on 37, A13 on 38, A14 on 39 and A11 on 40. |
| 2 | GND | Ground | Power | 0 V | Ground. |
| 3 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 4. The data bus is split: D4-D7 ascending on pins 3-6, then D3 down to D0 on 7-10. |
| 4 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 5. |
| 5 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 6. |
| 6 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 7. |
| 7 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 3. |
| 8 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 2. |
| 9 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 1. |
| 10 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 0. |
| 11 | VBB | Power | Power | -5 V (substrate bias) | Substrate bias. MUST be applied before (or with) the +12 V on pin 28 and must never be lost while +12 V is present, or the chip can be destroyed. On a bench supply bring -5 V up first and down last. |
| 12 | RESET | Control | Input | TTL, active high | Reset. ACTIVE HIGH — the opposite of the Z80. No slash. Held high for at least three clock cycles to reset the CPU. |
| 13 | HOLD | Control | Input | TTL, active high | Hold request. ACTIVE HIGH. Low tri-states the buses for DMA; the CPU acknowledges with HLDA (pin 21). |
| 14 | INT | Control | Input | TTL, active high | Interrupt request. ACTIVE HIGH. The CPU acknowledges with INTE (pin 16) high and asserts the status byte on the data bus. |
| 15 | PHI2 | Clock / Timing | Input | 12 V-swing clock | Phase 2 clock input. Two-phase 12 V-swing clock — NOT TTL. You cannot drive it from a 74-series oscillator; that is what the 8224 clock generator is for. |
| 16 | INTE | Control | Output | TTL | Interrupt Enable. High when interrupts are enabled by software. Reflects the state of the INTE flip-flop. |
| 17 | DBIN | Control | Output | TTL | Data Bus In. High when the CPU is reading data from the bus. Used by the 8228 system controller to gate the data bus direction. |
| 18 | /WR | Control | Output | TTL, active low | Active low. Write strobe. Low when the CPU is writing data to the bus. The only active-low pin on the 8080. |
| 19 | SYNC | Control | Output | TTL | Sync. High during the first clock cycle of each machine cycle, when the status byte is on the data bus. Check SYNC for activity each machine cycle. |
| 20 | VCC | Power | Power | +5 V | Logic supply. Decouple with 100 nF close to the pin. |
| 21 | HLDA | Control | Output | TTL | Hold Acknowledge. High in response to HOLD (pin 13), indicating the CPU has released the buses for DMA. |
| 22 | PHI1 | Clock / Timing | Input | 12 V-swing clock | Phase 1 clock input. Two-phase 12 V-swing clock — NOT TTL. Driven by the 8224 clock generator. |
| 23 | READY | Control | Input | TTL, active high | Ready. ACTIVE HIGH. Low stretches the machine cycle for slow memory. The CPU waits with WAIT (pin 24) high. |
| 24 | WAIT | Control | Output | TTL, active high | Wait. ACTIVE HIGH. High when the CPU is waiting for READY (pin 23) to return high. No slash. |
| 25 | A0 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 0. The address bus runs A0-A2 on pins 25-27. |
| 26 | A1 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 1. |
| 27 | A2 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 2. Pin 28 (+12 V) sits in the MIDDLE of the address bus, between A2 (pin 27) and A3 (pin 29). Probe along the bus assuming it is contiguous and you will put a probe on a 12 V rail. |
| 28 | VDD | Power | Power | +12 V | Positive supply. +12 V. Sits in the middle of the address bus between A2 (pin 27) and A3 (pin 29) — do not mistake it for an address line. |
| 29 | A3 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 3. The address bus continues A3-A9 on pins 29-35. |
| 30 | A4 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 4. |
| 31 | A5 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 5. |
| 32 | A6 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 6. |
| 33 | A7 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 7. |
| 34 | A8 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 8. |
| 35 | A9 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 9. |
| 36 | A15 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 15. The top of the address bus is scrambled: A15 on 36, A12 on 37, A13 on 38, A14 on 39, A11 on 40. |
| 37 | A12 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 12. |
| 38 | A13 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 13. |
| 39 | A14 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 14. |
| 40 | A11 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 11. |
Common uses and repair diagnostics
The Intel 8080A is the original 8-bit microprocessor and the best cautionary tale in this library. It needs THREE supply rails plus ground — pin 11 VBB at -5 V (substrate bias), pin 20 VCC at +5 V, pin 28 VDD at +12 V, pin 2 GND — and none of them where you would expect. The power sequencing matters: the -5 V on pin 11 must be applied before (or with) the +12 V on pin 28 and must never be lost while +12 V is present, or the chip can be destroyed. On a bench supply that means bringing -5 V up first and down last. This is the single most important thing on the page — lead with it.
The Intel 8080A is the original 8-bit microprocessor and the best cautionary tale in this library. It needs THREE supply rails plus ground — pin 11 VBB at -5 V (substrate bias), pin 20 VCC at +5 V, pin 28 VDD at +12 V, pin 2 GND — and none of them where you would expect. The power sequencing is a genuine repair hazard: the -5 V on pin 11 must be applied before (or with) the +12 V on pin 28 and must never be lost while +12 V is present, or the chip can be destroyed. On a bench supply that means bringing -5 V up first and down last.
The address bus has no pattern at all: A10 alone on pin 1, A0-A2 on 25-27, A3-A9 on 29-35, then A15 on 36, A12 on 37, A13 on 38, A14 on 39 and A11 on 40. Pin 28 (+12 V) sits in the middle of the address bus between A2 and A3 — probe along the bus assuming it is contiguous and you will put a probe on a 12 V rail. The data bus is also split: D4-D7 ascending on pins 3-6, then D3 down to D0 on 7-10.
RESET (pin 12), HOLD (pin 13), INT (pin 14), READY (pin 23) and WAIT (pin 24) are all ACTIVE HIGH — the opposite of the Z80 equivalents. Only /WR (pin 18) is active low. PHI1 (pin 22) and PHI2 (pin 15) need a two-phase 12 V-swing clock, NOT TTL — you cannot drive them from a 74-series oscillator; that is what the 8224 clock generator is for. A usable 8080 system also needs the 8228 system controller to decode the status byte. Three chips to do what one Z80 does — which is precisely why the Z80 took the market.
Used in the Altair 8800, IMSAI 8080, SOL-20 and the first generation of CP/M machines. The Soviet KR580VM80A is a clone and a valid substitute.
- Measure all three rails before anything else: pin 11 VBB at -5 V, pin 20 VCC at +5 V, pin 28 VDD at +12 V. Confirm -5 V is present.
- A missing -5 V rail gives bizarre, partial, heat-dependent behaviour rather than a clean failure — do not assume the chip is dead until the rails are confirmed.
- Check SYNC (pin 19) for activity each machine cycle. No SYNC means the CPU is not cycling.
- Remember the power sequencing: -5 V up first and down last. Losing -5 V while +12 V is present can destroy the chip.
- Pin 28 is +12 V in the middle of the address bus. Do not probe the address bus assuming it is contiguous.