Pinout diagram
Used in Retro Machine Hubs
Click any system badge below to jump directly to its dedicated repair, schematic, and diagnostic Machine Hub:
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description | Expected Signal |
|---|---|---|---|---|---|---|
| 1 | VPP (A15 on 27512) | Power | Input | +5 V in Read mode | 27128/27256: Programming Voltage VPP (MUST be tied to +5V VCC in read mode!). On a 64KB 27C512/W27C512, Pin 1 is Address A15 — lift Pin 1 and wire to a SPDT toggle switch (+5V via 4.7k vs GND) for a dual-OS / DiagROM switch! | |
| 2 | A12 | Address Bus | Input | TTL | Address bus bit 12. | |
| 3 | A7 | Address Bus | Input | TTL | Address bus bit 7 (A7 down to A0 descend sequentially down Pins 3–10). | |
| 4 | A6 | Address Bus | Input | TTL | Address bus bit 6. | |
| 5 | A5 | Address Bus | Input | TTL | Address bus bit 5. | |
| 6 | A4 | Address Bus | Input | TTL | Address bus bit 4. | |
| 7 | A3 | Address Bus | Input | TTL | Address bus bit 3. | |
| 8 | A2 | Address Bus | Input | TTL | Address bus bit 2. | |
| 9 | A1 | Address Bus | Input | TTL | Address bus bit 1. | |
| 10 | A0 | Address Bus | Input | TTL | Address bus bit 0 (LSB). | |
| 11 | D0 | Data Bus | Tri-state output | TTL, tri-state | Data bus bit 0 (LSB). | |
| 12 | D1 | Data Bus | Tri-state output | TTL, tri-state | Data bus bit 1. | |
| 13 | D2 | Data Bus | Tri-state output | TTL, tri-state | Data bus bit 2. | |
| 14 | GND (VSS) | Ground | Power | 0 V | 0 V System Ground. | |
| 15 | D3 | Data Bus | Tri-state output | TTL, tri-state | Data bus bit 3. | |
| 16 | D4 | Data Bus | Tri-state output | TTL, tri-state | Data bus bit 4. | |
| 17 | D5 | Data Bus | Tri-state output | TTL, tri-state | Data bus bit 5. | |
| 18 | D6 | Data Bus | Tri-state output | TTL, tri-state | Data bus bit 6. | |
| 19 | D7 | Data Bus | Tri-state output | TTL, tri-state | Data bus bit 7 (MSB). | |
| 20 | /CE (/ROME) | Control | Input | TTL, active low | Active-low Chip Enable. Driven by Gate Array Pin 23 (/ROME) on the Amstrad CPC 464. | |
| 21 | A10 | Address Bus | Input | TTL | Address bus bit 10. | |
| 22 | /OE | Control | Input | TTL, active low | Active-low Output Enable (tied to /CE or GND on the CPC 464). | |
| 23 | A11 | Address Bus | Input | TTL | Address bus bit 11. | |
| 24 | A9 | Address Bus | Input | TTL | Address bus bit 9. | |
| 25 | A8 | Address Bus | Input | TTL | Address bus bit 8. | |
| 26 | A13 | Address Bus | Input | TTL | Address bus bit 13 (16 KB select bit on both 27128 and 27256; NC on 8KB 2764). | |
| 27 | A14 (27256) | /PGM (27128) | Address Bus | Input | TTL | On 32KB 27256 & Amstrad 40009: Address bit 14 (Driven by Z80 A14/A15 to switch between Lower OS at $0000 and Upper BASIC at $C000!). On 16KB 27128: /PGM (must be tied HIGH to +5V for read mode). | |
| 28 | VCC (+5V) | Power | Power | +5.0 V DC | +5.0 V DC supply rail. Decouple with 100 nF ceramic capacitor. |
Common uses and repair diagnostics
In the Amstrad CPC 464, both the 16 KB Lower Operating System Firmware ($0000–$3FFF) and the 16 KB Upper Locomotive BASIC 1.0 interpreter ($C000–$FFFF) reside inside a single 32 KB (32,768 x 8-bit) 28-pin mask ROM at IC103 (Amstrad Part No. 40009, or 40013 on European keyboards). Unlike Commodore's non-standard 24-pin mask ROMs, Amstrad wired IC103 to the standard JEDEC 28-pin 27256 pinout: the Gate Array drives Pin 20 (/ROME) low whenever either ROM window is enabled, and uses Pin 27 (A14) to select the lower 16 KB half (A14 = 0 for OS at $0000–$3FFF) or the upper 16 KB half (A14 = 1 for Locomotive BASIC at $C000–$FFFF). As a result, a standard 27C256 UV EPROM (or W27C512 EEPROM) plugs directly into IC103 with zero adapter sockets or track cuts!
Used as IC103 in the Amstrad CPC 464 (Part 40009 = 32 KB combined OS + Locomotive BASIC 1.0), IC103 in the CPC 6128 (Part 40025 = 32 KB OS + BASIC 1.1), and as the 16 KB AMSDOS ROM (27128 / Part 40015) inside the DDI-1 Disc Interface and CPC 664/6128.
If you only have a 64 KB W27C512 EEPROM on your bench and want to replace a dead 32 KB 40009 ROM in a CPC 464 with zero modifications, simply concatenate the 32 KB image twice (copy /b cpc464.rom + cpc464.rom cpc512.bin) and drop the programmed W27C512 straight into IC103 — since the CPC 464 ties Pin 1 to +5 V, the upper 32 KB bank ($8000–$FFFF) will be selected automatically!
- If a CPC 464 shows a black or solid border-less screen and has a healthy 4 MHz clock on Z80 Pin 6, scope IC103 Pin 20 (/CE) for active-low pulses. Remember: the 6845 CRTC has no power-on default timing — the Z80 MUST read the initialization table out of IC103 OS ROM before the CRTC can output HSYNC/VSYNC!
- Verify Pin 1 (VPP) and Pin 28 (VCC) sit at +5.0 V.
- Check Pin 27 (A14) toggles between 0 V (Lower OS ROM fetch at $0000–$3FFF) and +5 V (Upper BASIC ROM fetch at $C000–$FFFF).
Datasheets and references
- ST M27C256B 32K x 8 UV EPROM Datasheet (PDF)
- Winbond W27C512 64K x 8 Electrically Erasable PROM Datasheet