Pinout diagram
Used in Retro Machine Hubs
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Summary specifications
Technology
NMOS
Operating Voltage
+5 V +/-5% (VCC pin 40, GND pin 20)
Master Clock
4.0 MHz on Pin 19 (CLK) for standard 250 kbps DD drives
CPU Interface
1 address pin (A0 on Pin 5: 0 = Main Status Register, 1 = Data/Command FIFO)
Data Separator
External PLL/counter (e.g. SED9420CAC) feeding Pin 23 (RDDATA) and Pin 22 (RCLK)
Drive Selects
2-bit binary output US0/US1 (Pins 38-39) selecting up to 4 drives
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | RST | Control | Input | TTL, active high | Reset input — ACTIVE HIGH (1 = Reset)! |
| 2 | /RD | Control | Input | TTL, active low | CPU Read strobe. |
| 3 | /WR | Control | Input | TTL, active low | CPU Write strobe. |
| 4 | /CS | Control | Input | TTL, active low | Chip Select input (decoded at &FB7E/&FB7F on CPC 6128; &2FFD/&3FFD on Spectrum +3). |
| 5 | A0 | Address Bus | Input | TTL | Register Select: 0 = Main Status Register (Read Only), 1 = Data/Command/Result FIFO. |
| 6 | DB0 | Data Bus | Bidirectional | TTL | CPU Data bus bit 0. |
| 7 | DB1 | Data Bus | Bidirectional | TTL | CPU Data bus bit 1. |
| 8 | DB2 | Data Bus | Bidirectional | TTL | CPU Data bus bit 2. |
| 9 | DB3 | Data Bus | Bidirectional | TTL | CPU Data bus bit 3. |
| 10 | DB4 | Data Bus | Bidirectional | TTL | CPU Data bus bit 4. |
| 11 | DB5 | Data Bus | Bidirectional | TTL | CPU Data bus bit 5. |
| 12 | DB6 | Data Bus | Bidirectional | TTL | CPU Data bus bit 6. |
| 13 | DB7 | Data Bus | Bidirectional | TTL | CPU Data bus bit 7. |
| 14 | DRQ | Control | Output | TTL | DMA Request output (unused on CPC 6128 / Spectrum +3, which poll MSR Bit 7 RQM in Z80 software!). |
| 15 | /DACK | Control | Input | TTL, active low | DMA Acknowledge input (tied high on non-DMA Z80 systems). |
| 16 | TC | Control | Input | TTL, active high | Terminal Count input (pulsed high by I/O port decode on CPC/Spectrum +3 to end sector transfer). |
| 17 | IDX | I/O | Input | TTL | Index Pulse input from floppy drive. |
| 18 | INT | Control | Output | TTL, active high | Interrupt output. |
| 19 | CLK | Clock / Timing | Input | TTL 4.0 MHz | 4.0 MHz master FDC clock input. |
| 20 | GND | Ground | Power | 0 V | System ground (0 V). |
| 21 | WCLK | Clock / Timing | Input | TTL clock | Write Clock input (500 kHz MFM / 250 kHz FM reference clock). |
| 22 | RCLK | Clock / Timing | Input | TTL clock | Read Clock Window input from external data separator (SED9420 Pin 17). |
| 23 | RDDATA | I/O | Input | TTL | Separated Read Data pulses from external data separator (SED9420 Pin 18). |
| 24 | HS (HDSEL) | I/O | Output | TTL | Head Select (Side 0 / Side 1) output. |
| 25 | WE | I/O | Output | TTL | Write Enable (Write Gate) output to floppy drive. |
| 26 | MFM | Control | Output | TTL | MFM (1) / FM (0) mode indicator output to SED9420 data separator. |
| 27 | HD | I/O | Output | TTL | High Density / Head Load output. |
| 28 | FLT/TRK0 | I/O | Input | TTL | Multiplexed Drive Fault / Track 00 sensor input! |
| 29 | WP/TS | I/O | Input | TTL | Multiplexed Write Protect / Two-Sided sensor input! |
| 30 | WRDATA | I/O | Output | TTL | MFM Write Data pulse output to floppy drive. |
| 31 | PS0 | Control | Output | TTL | Write Precompensation shift select bit 0. |
| 32 | PS1 | Control | Output | TTL | Write Precompensation shift select bit 1. |
| 33 | FR/STP | I/O | Output | TTL | Fault Reset / Stepper Motor STEP pulse output! |
| 34 | LCT/DIR | I/O | Output | TTL | Low Current / Stepper Direction output! |
| 35 | RW/SEEK | Control | Output | TTL | Read-Write / Seek mode multiplex control (switches Pins 28, 29, 33, 34 between Seek signals and Read/Write signals!). |
| 36 | HDL | I/O | Output | TTL | Head Load output. |
| 37 | RDY | I/O | Input | TTL | Drive Ready input (from Shugart Pin 34! Why PC 3.5-inch drives on a CPC 6128 or Spectrum +3 need Pin 34 READY enabled or tied low!). |
| 38 | US0 | I/O | Output | TTL | Unit Select bit 0 (0 = Drive A, 1 = Drive B). |
| 39 | US1 | I/O | Output | TTL | Unit Select bit 1. |
| 40 | VCC (+5V) | Power | Power | +5 V | +5 V main supply. |
Common uses and repair diagnostics
Jointly developed by NEC (uPD765A) and Intel (8272A) and second-sourced by Zilog (Z0765A), this 40-pin DIP is the floppy disk controller that powered the IBM PC/XT, Amstrad CPC 664, CPC 6128, Amstrad PCW, and Sinclair ZX Spectrum +3. Unlike the 28-pin WD1772 (which has 4 registers and an internal data separator), the 40-pin uPD765A exposes ONLY TWO CPU I/O registers selected by A0 (Pin 5): A0=0 reads the Main Status Register (MSR), and A0=1 reads/writes multi-byte Command, Execution, and Result packets through a single Data FIFO port! It also requires an external Data Separator (such as the 24-pin SED9420CAC on the CPC 6128 and Spectrum +3) to split the raw MFM stream into RDDATA (Pin 23) and RCLK (Pin 22).
Used in the Amstrad CPC 664, CPC 6128, Amstrad PCW 8256/8512, Sinclair ZX Spectrum +3, IBM PC/XT, and Kaypro / CP/M systems.
- Look closely at Pin 37 (RDY): the uPD765A refuses to execute Read/Write commands unless Pin 37 (RDY) is active! When connecting a Gotek or PC 3.5-inch drive to a CPC 6128 or ZX Spectrum +3, you MUST configure Pin 34 of the floppy ribbon for READY (or ground Pin 34) — otherwise AMSDOS/Plus3DOS reports 'Drive A: Read Fail / Drive Not Ready'!
- Remember that 95% of 'Disc Missing' faults on a CPC 6128 or Spectrum +3 are a stretched 3-inch rubber drive belt (`71mm x 0.6mm x 2.8mm`), not a bad uPD765A chip!