Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | /OE | Control | Input | TTL, 0 V / 5 V, active low | Output enable, active low. When low, the registered Q outputs drive the bus; when high, the Q outputs are high impedance. The flip-flops keep holding regardless of OE. |
| 2 | 1Q | I/O | Tri-state output | TTL 3-state | Registered output 1. Takes the 1D level on the rising edge of CLK; high impedance when OE is high. |
| 3 | 1D | I/O | Input | TTL, 0 V / 5 V | Data input 1. |
| 4 | 2D | I/O | Input | TTL, 0 V / 5 V | Data input 2. |
| 5 | 2Q | I/O | Tri-state output | TTL 3-state | Registered output 2. Takes the 2D level on the rising edge of CLK. |
| 6 | 3Q | I/O | Tri-state output | TTL 3-state | Registered output 3. Takes the 3D level on the rising edge of CLK. |
| 7 | 3D | I/O | Input | TTL, 0 V / 5 V | Data input 3. |
| 8 | 4D | I/O | Input | TTL, 0 V / 5 V | Data input 4. |
| 9 | 4Q | I/O | Tri-state output | TTL 3-state | Registered output 4. Takes the 4D level on the rising edge of CLK. |
| 10 | GND | Ground | Power | 0 V | Ground return for all eight flip-flops. |
| 11 | CLK | Clock / Timing | Input | TTL, rising edge | Clock, positive-edge triggered. On every low-to-high transition, each Q output takes the level of its D input. This is the pin that distinguishes the 374 from the 373, which uses pin 11 as a level-sensitive latch enable. |
| 12 | 5Q | I/O | Tri-state output | TTL 3-state | Registered output 5. Takes the 5D level on the rising edge of CLK. |
| 13 | 5D | I/O | Input | TTL, 0 V / 5 V | Data input 5. |
| 14 | 6D | I/O | Input | TTL, 0 V / 5 V | Data input 6. |
| 15 | 6Q | I/O | Tri-state output | TTL 3-state | Registered output 6. Takes the 6D level on the rising edge of CLK. |
| 16 | 7Q | I/O | Tri-state output | TTL 3-state | Registered output 7. Takes the 7D level on the rising edge of CLK. |
| 17 | 7D | I/O | Input | TTL, 0 V / 5 V | Data input 7. |
| 18 | 8D | I/O | Input | TTL, 0 V / 5 V | Data input 8. |
| 19 | 8Q | I/O | Tri-state output | TTL 3-state | Registered output 8. Takes the 8D level on the rising edge of CLK. |
| 20 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The 74LS374 is the octal edge-triggered D-type flip-flop with 3-state outputs. On every rising edge of the clock (CLK) on pin 11, the eight Q outputs take the eight D inputs and hold them; the active-low output enable (OE) on pin 1 then gates those registered levels onto a shared bus. It is the part you reach for whenever a board needs to capture a whole byte on a single clock edge and present it later — a registered output port, a pipeline stage, a data latch that must not be transparent. The 74LS374 occupies the same pin positions as the 74LS373, and the two are a common substitution mistake: the 374 clocks on the rising edge of pin 11, the 373 latches on the level of pin 11.
The 74LS374 is the registered output port on boards that need to capture a whole byte on one clock edge and hold it steady for the next cycle. It builds output ports that latch the data byte on the write strobe, pipeline stages that hold intermediate results between CPU and peripheral, and the data registers that drive LED columns or stepper coils from a microprocessor bus. The 3-state outputs let several 74LS374s sit on the same bus and take turns driving it. The 74HC374 and 74HCT374 are the CMOS equivalents and share the same pinout. The 74LS374 and 74LS373 occupy identical pin positions and differ only in what pin 11 does: on the 374 it is an edge-triggered clock, on the 373 it is a level-sensitive latch enable. The two are a common substitution mistake — a 374 in a 373 socket misses the transparent window the CPU relies on, and the captured address is wrong.
- With power off, probe pin 20 (VCC) to pin 10 (GND) for a low-ohms supply rail; a dead short or open points to a decoupling capacitor or the chip itself.
- Power up and check pin 20 sits at 4.75 to 5.25 V. A sagging rail can make a 3-state output float when it should drive, which on a bus looks like a stuck line.
- Drive a D input, clock CLK with a clean rising edge and check the matching Q takes the D level. A Q that does not change suggests a dead flip-flop or a floating D input.
- Toggle OE and check the Q outputs go high impedance when OE is high (read with a pull-up and a pull-down in turn). A Q that drives when OE is high means a failed 3-state buffer.
- If the captured byte is wrong, scope CLK — a slow or bouncing edge can double-clock the flip-flops and capture the data twice. Confirm the board has the 74LS374 and not the 74LS373 fitted: the two share a pinout but respond to pin 11 differently.