Pinout diagram
Used in Retro Machine Hubs
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Summary specifications
Technology
HMOS-2
Operating Voltage
+5 V +/-5% (VDD pins 5 and 29, VSS pins 12, 24 and 48)
Dot Clock
16.0 MHz input on Pin 2 (CLK)
Video Output
Digital TTL RGBI (Red, Green, Blue, Intensity -> 16 colours) + Monochrome video
Private VRAM
16 KB (2x 4416) or 64 KB (2x 4464) via multiplexed RA0-RA7
CPU Interface
2 registers only (RS pin 18 selects $D600 Status/Index or $D601 Data)
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | CCLK | Clock / Timing | Output | TTL clock | Character Clock output (2 MHz / 1 MHz). |
| 2 | CLK | Clock / Timing | Input | TTL 16 MHz | 16.0 MHz master dot clock input. |
| 3 | /DISPEN | Control | Output | TTL | Display Enable output. |
| 4 | /CAS | Control | Output | TTL, active low | Private VRAM Column Address Strobe. |
| 5 | VDD1 | Power | Power | +5 V | Primary +5 V supply (also connect Pin 29). |
| 6 | /RAS | Control | Output | TTL, active low | Private VRAM Row Address Strobe. |
| 7 | /WE | Control | Output | TTL, active low | Private VRAM Write Enable. |
| 8 | RA0 | Address Bus | Output | TTL | VRAM multiplexed address bit 0. |
| 9 | RA1 | Address Bus | Output | TTL | VRAM multiplexed address bit 1. |
| 10 | RA2 | Address Bus | Output | TTL | VRAM multiplexed address bit 2. |
| 11 | RA3 | Address Bus | Output | TTL | VRAM multiplexed address bit 3. |
| 12 | VSS1 | Ground | Power | 0 V | Ground. |
| 13 | RA4 | Address Bus | Output | TTL | VRAM multiplexed address bit 4. |
| 14 | RA5 | Address Bus | Output | TTL | VRAM multiplexed address bit 5. |
| 15 | RA6 | Address Bus | Output | TTL | VRAM multiplexed address bit 6. |
| 16 | RA7 | Address Bus | Output | TTL | VRAM multiplexed address bit 7 (used when upgraded to 64 KB 4464 VRAM!). |
| 17 | R/W | Control | Input | TTL | CPU Read/Write input. |
| 18 | RS | Address Bus | Input | TTL | Register Select (connected to CPU A0: 0 = $D600 Address/Status, 1 = $D601 Data). |
| 19 | /CS | Control | Input | TTL, active low | Chip Select ($D600-$D601). |
| 20 | PHI2 | Clock / Timing | Input | TTL clock | System PHI2 bus clock from 8502. |
| 21 | D7 | Data Bus | Bidirectional | TTL | CPU data bus bit 7. |
| 22 | D6 | Data Bus | Bidirectional | TTL | CPU data bus bit 6. |
| 23 | D5 | Data Bus | Bidirectional | TTL | CPU data bus bit 5. |
| 24 | VSS2 | Ground | Power | 0 V | Ground. |
| 25 | D4 | Data Bus | Bidirectional | TTL | CPU data bus bit 4. |
| 26 | D3 | Data Bus | Bidirectional | TTL | CPU data bus bit 3. |
| 27 | D2 | Data Bus | Bidirectional | TTL | CPU data bus bit 2. |
| 28 | D1 | Data Bus | Bidirectional | TTL | CPU data bus bit 1. |
| 29 | VDD2 | Power | Power | +5 V | Secondary +5 V supply. |
| 30 | D0 | Data Bus | Bidirectional | TTL | CPU data bus bit 0. |
| 31 | RD7 | Data Bus | Bidirectional | TTL | Private VRAM data bit 7. |
| 32 | RD6 | Data Bus | Bidirectional | TTL | Private VRAM data bit 6. |
| 33 | RD5 | Data Bus | Bidirectional | TTL | Private VRAM data bit 5. |
| 34 | RD4 | Data Bus | Bidirectional | TTL | Private VRAM data bit 4. |
| 35 | RD3 | Data Bus | Bidirectional | TTL | Private VRAM data bit 3. |
| 36 | RD2 | Data Bus | Bidirectional | TTL | Private VRAM data bit 2. |
| 37 | RD1 | Data Bus | Bidirectional | TTL | Private VRAM data bit 1. |
| 38 | RD0 | Data Bus | Bidirectional | TTL | Private VRAM data bit 0. |
| 39 | /HSYNC | I/O | Output | TTL | Horizontal Sync output (to 9-pin RGBI port Pin 8). |
| 40 | /VSYNC | I/O | Output | TTL | Vertical Sync output (to 9-pin RGBI port Pin 9). |
| 41 | /LP | I/O | Input | TTL | Light Pen strobe input. |
| 42 | R | I/O | Output | TTL | Digital RED video output (to RGBI Pin 3). |
| 43 | G | I/O | Output | TTL | Digital GREEN video output (to RGBI Pin 4). |
| 44 | B | I/O | Output | TTL | Digital BLUE video output (to RGBI Pin 5). |
| 45 | I | I/O | Output | TTL | Digital INTENSITY output (to RGBI Pin 6; also mixed for 80-col monochrome on Pin 7). |
| 46 | INIT | Control | Input | TTL | Initialization / Reset input. |
| 47 | DRAW | Control | Output | TTL | Internal block-copy / fill busy indicator. |
| 48 | VSS3 | Ground | Power | 0 V | Ground. |
Common uses and repair diagnostics
The MOS 8563 (HMOS-2) and 8568 (used in the cost-reduced C128DCR) generate the Commodore 128's crisp 640x200 / 80x25 digital RGBI (CGA-compatible) 80-column display for the Z80 CP/M and BASIC 7.0 modes. Just like the TMS9918A, the 8563's 16 KB (two 4416 DRAMs on flat C128) or 64 KB (two 4464 DRAMs on C128DCR) of Video RAM sits on a private bus (RA0-RA7, RD0-RD7) that the 8502/Z80 CPU can only read and write indirectly through two I/O ports: $D600 (Address/Status) and $D601 (Data).
Used exclusively in the Commodore 128 (8563R7A/R8/R9) and C128DCR (8568). Upgrading a flat C128 from 16 KB to 64 KB of 80-column VRAM is as simple as replacing the two 18-pin 4416 DRAMs (U22 and U23) with two 4464 (64Kx4) DRAMs and setting internal Register 28 Bit 4!
- If 40-column VIC-II video works normally on a C128, but the 80-column RGBI output is dead, check the 16 MHz dot clock on Pin 2 (CLK) and /HSYNC (Pin 39) + /VSYNC (Pin 40).
- Garbled characters in 80-column mode only (while 40-column mode is fine) point directly to the two private 4416/4464 VRAM chips (U22 = RD0-RD3, U23 = RD4-RD7)!
- Attach a small heatsink to the 48-pin 8563 VDC — early 8563R7A revisions run hot inside the RF shield.