Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | 1A | I/O | Input | TTL, 0 V / 5 V | Gate 1, input A. An unused input must be tied to a rail, not left floating. |
| 2 | 1B | I/O | Input | TTL, 0 V / 5 V | Gate 1, input B. |
| 3 | 1Y | I/O | Output | TTL totem-pole | Gate 1 output. High when 1A and 1B differ; low when they are equal. |
| 4 | 2A | I/O | Input | TTL, 0 V / 5 V | Gate 2, input A. |
| 5 | 2B | I/O | Input | TTL, 0 V / 5 V | Gate 2, input B. |
| 6 | 2Y | I/O | Output | TTL totem-pole | Gate 2 output. High when 2A and 2B differ. |
| 7 | GND | Ground | Power | 0 V | Ground return for all four gates. |
| 8 | 3Y | I/O | Output | TTL totem-pole | Gate 3 output. High when 3A and 3B differ. |
| 9 | 3A | I/O | Input | TTL, 0 V / 5 V | Gate 3, input A. |
| 10 | 3B | I/O | Input | TTL, 0 V / 5 V | Gate 3, input B. |
| 11 | 4Y | I/O | Output | TTL totem-pole | Gate 4 output. High when 4A and 4B differ. |
| 12 | 4A | I/O | Input | TTL, 0 V / 5 V | Gate 4, input A. |
| 13 | 4B | I/O | Input | TTL, 0 V / 5 V | Gate 4, input B. |
| 14 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The 74LS86 holds four independent 2-input XOR gates in a 14-pin DIP, and like the 74LS08 and 74LS32 it follows the standard 74LS00 pinout: inputs first, output third, on each group, with outputs on pins 3, 6, 8 and 11. The XOR is the part you reach for when a signal needs to be inverted under control — feed one input high and the gate inverts the other; feed it low and the gate passes it through. That true/complement behaviour is what makes the XOR the building block of adders, comparators and parity generators.
The 74LS86 is the standard XOR glue on boards that need a controllable invert or a parity check. With one input tied high it becomes a programmable inverter; with both inputs driven it becomes a comparator that flags when two signals differ. It builds the sum bit of a half-adder, the parity tree that detects single-bit errors, and the true/complement selectors that some address decoders use to cover two ranges with one gate. The 74HC86 and 74HCT86 are the CMOS equivalents and share the same pinout.
- With power off, probe pin 14 (VCC) to pin 7 (GND) for a low-ohms supply rail; a dead short or open points to a decoupling capacitor or the chip itself.
- Power up and check pin 14 sits at 4.75 to 5.25 V. A sagging rail pulls the gate outputs out of spec and is often the real fault, not the gate.
- Tie one input high and drive the other: the output must invert the driven input. Tie the same input low and drive again: the output must follow the driven input. A gate that does neither is dead.
- Tie both inputs of an unused gate to GND; a floating LS input drifts high and, on an XOR, makes the output follow the noise on the other input.
- If several gates misbehave at once, suspect the supply decoupling first — a 74LS86 with no bypass capacitor can glitch the whole board when its outputs switch.