Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | NC | No Connect | Not connected | No connect | No connect. On the 2764 EPROM this pin is VPP (programming voltage); on the 62256 SRAM it becomes A14. |
| 2 | A12 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 12. A12 is alone on pin 2, then A7 down to A0 descend on pins 3-10. |
| 3 | A7 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 7. The main address block descends: A7, A6, A5, A4, A3, A2, A1, A0 on pins 3-10. |
| 4 | A6 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 6. |
| 5 | A5 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 5. |
| 6 | A4 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 4. |
| 7 | A3 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 3. |
| 8 | A2 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 2. |
| 9 | A1 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 1. |
| 10 | A0 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 0. |
| 11 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bit 0. The data bus is split either side of the ground pin: D0, D1, D2 on pins 11-13, GND on 14, then D3 to D7 on pins 15-19. |
| 12 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bit 1. |
| 13 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bit 2. |
| 14 | GND | Ground | Power | 0 V | Ground. The data bus splits either side of this pin. |
| 15 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bit 3. |
| 16 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bit 4. |
| 17 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bit 5. |
| 18 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bit 6. |
| 19 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bit 7. |
| 20 | /CS1 | Control | Input | TTL, active low | Active low. Chip Select 1. Both /CS1 low AND CS2 (pin 26) high must be satisfied for the chip to respond. On the 2764 this pin is /CE (same role). |
| 21 | A10 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 10. The upper address bits are scattered: A10 (21), A11 (23), A9 (24), A8 (25). |
| 22 | /OE | Control | Input | TTL, active low | Active low. Output Enable. Low drives the data bus. Ground this and wire the CPU R/W to /WE for a 6500-style bus. |
| 23 | A11 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 11. |
| 24 | A9 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 9. |
| 25 | A8 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 8. |
| 26 | CS2 | Control | Input | TTL, active high | Chip Select 2, active HIGH. Both /CS1 (pin 20) low AND CS2 high must be satisfied. Leave CS2 floating or low and the chip never responds — the commonest reason a newly fitted 6264 appears dead. On the 2764 this pin is no-connect; on the 62256 it becomes A13. |
| 27 | /WE | Control | Input | TTL, active low | Active low. Write Enable. Low writes the data bus into the selected address. On the 2764 this pin is /PGM (program strobe). |
| 28 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. CMOS versions draw microamps in standby, which is why 6264s turn up battery-backed for save RAM. |
Common uses and repair diagnostics
The 6264 is an 8192-word x 8-bit static RAM in the JEDEC 28-pin byte-wide package. The headline trap is the two chip selects of opposite polarity: /CS1 (pin 20) active LOW and CS2 (pin 26) active HIGH. Both must be satisfied. Leave CS2 floating or low and the chip never responds — the commonest reason a newly fitted 6264 appears dead. This is the JEDEC 28-pin byte-wide standard, and the layout is worth learning once because the 2764 EPROM, the 62256 SRAM and the 27128/27256 EPROMs all follow it. See the 2764 page for the four-pin difference.
The 6264 is an 8192-word x 8-bit static RAM in the JEDEC 28-pin byte-wide package. Used in the NES and Famicom cartridges (as work/save RAM), the Amstrad CPC, the MSX, arcade boards, and as the RAM upgrade in countless 8-bit designs. Fully static, single +5 V, no refresh. CMOS versions draw microamps in standby, which is why 6264s turn up battery-backed for save RAM.
The headline trap is the two chip selects of opposite polarity: /CS1 (pin 20) active LOW and CS2 (pin 26) active HIGH. Both must be satisfied. Leave CS2 floating or low and the chip never responds, which is the commonest reason a newly fitted 6264 appears dead. This is the JEDEC 28-pin byte-wide standard, and the layout is worth learning once because the 2764 EPROM, the 62256 SRAM and the 27128/27256 EPROMs all follow it. See the 2764 page for the four-pin difference.
The 62256 (32K x 8) is nearly a drop-in: pin 1 becomes A14 and pin 26 becomes A13 instead of CS2. So on a board that ties CS2 high you can often fit a 62256 and address the extra space, but on a board that actively drives CS2 you cannot. Address pins are split and not in order: A12 alone on pin 2, then A7 down to A0 descending on pins 3-10, then A10 (21), A11 (23), A9 (24), A8 (25) scattered on the other side. The data bus is split either side of the ground pin: D0, D1, D2 on 11-13, GND on 14, then D3 to D7 on 15-19.
Separate /OE (22) and /WE (27) give it an 8080-style bus, but grounding /OE and wiring the CPU's R/W to /WE converts it to a 6500-style bus — which is how it is used in 6502 systems. That trick is worth stating; it is why one part suits both families.
- Confirm CS2 (pin 26) is high and /CS1 (pin 20) is being driven low on access. A floating CS2 is the commonest reason a newly fitted 6264 appears dead.
- Write and read back a walking-bit pattern. A single stuck data bit is a failed chip.
- Faults confined to a region of the range point at an address line or track, not the chip itself.
- Check VCC on pin 28 and GND on pin 14 — the standard 28-pin arrangement.
- For battery-backed save RAM, check the battery and the CS2 pull-up path before condemning the chip.