Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | /1G | Control | Input | TTL, 0 V / 5 V, active low | Group 1 output enable, active low. When low, group 1 Y outputs follow the 1A inputs; when high, the 1Y outputs are high impedance. |
| 2 | 1A1 | I/O | Input | TTL, 0 V / 5 V | Group 1, input 1. |
| 3 | 2Y4 | I/O | Tri-state output | TTL 3-state | Group 2, output 4. Follows 2A4 when 2G is low; high impedance when 2G is high. |
| 4 | 1A2 | I/O | Input | TTL, 0 V / 5 V | Group 1, input 2. |
| 5 | 2Y3 | I/O | Tri-state output | TTL 3-state | Group 2, output 3. Follows 2A3 when 2G is low; high impedance when 2G is high. |
| 6 | 1A3 | I/O | Input | TTL, 0 V / 5 V | Group 1, input 3. |
| 7 | 2Y2 | I/O | Tri-state output | TTL 3-state | Group 2, output 2. Follows 2A2 when 2G is low; high impedance when 2G is high. |
| 8 | 1A4 | I/O | Input | TTL, 0 V / 5 V | Group 1, input 4. |
| 9 | 2Y1 | I/O | Tri-state output | TTL 3-state | Group 2, output 1. Follows 2A1 when 2G is low; high impedance when 2G is high. |
| 10 | GND | Ground | Power | 0 V | Ground return for both groups. |
| 11 | 2A1 | I/O | Input | TTL, 0 V / 5 V | Group 2, input 1. |
| 12 | 1Y4 | I/O | Tri-state output | TTL 3-state | Group 1, output 4. Follows 1A4 when 1G is low; high impedance when 1G is high. |
| 13 | 2A2 | I/O | Input | TTL, 0 V / 5 V | Group 2, input 2. |
| 14 | 1Y3 | I/O | Tri-state output | TTL 3-state | Group 1, output 3. Follows 1A3 when 1G is low; high impedance when 1G is high. |
| 15 | 2A3 | I/O | Input | TTL, 0 V / 5 V | Group 2, input 3. |
| 16 | 1Y2 | I/O | Tri-state output | TTL 3-state | Group 1, output 2. Follows 1A2 when 1G is low; high impedance when 1G is high. |
| 17 | 2A4 | I/O | Input | TTL, 0 V / 5 V | Group 2, input 4. |
| 18 | 1Y1 | I/O | Tri-state output | TTL 3-state | Group 1, output 1. Follows 1A1 when 1G is low; high impedance when 1G is high. |
| 19 | /2G | Control | Input | TTL, 0 V / 5 V, active low | Group 2 output enable, active low. When low, group 2 Y outputs follow the 2A inputs; when high, the 2Y outputs are high impedance. |
| 20 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The 74LS244 is the octal 3-state buffer that drives the address and data buses on most 8-bit and 16-bit boards. It is organised as two independent 4-bit groups, each with its own active-low enable, and the two groups are interleaved down the package — A inputs and Y outputs of the two nibbles alternate down both sides, which is the trap for anyone who assumes it has the clean inputs-one-side, outputs-the-other arrangement of the 74LS245. When the enable is low the buffer passes data from A to Y; when high the Y outputs go to the high-impedance state, which is what lets the 74LS244 sit on a shared bus without contention.
The 74LS244 is the bus driver on boards that need to fan out an address or data line to many loads without loading down the source. It drives the address bus from the CPU to the memory and I/O, isolates a weak peripheral output from the main bus, and provides the extra sink current that long bus runs or many receivers demand. The two independent 4-bit groups let one 74LS244 drive the low and high nibbles of a bus from separate enables, which is useful on boards that gate the two halves of the address separately. The 74HC244 and 74HCT244 are the CMOS equivalents and share the same pinout. Note that the 74LS244 is not a drop-in for the 74LS245 — the 245 is a bidirectional transceiver with a direction pin, the 244 is unidirectional, and the pin assignments are different.
- With power off, probe pin 20 (VCC) to pin 10 (GND) for a low-ohms supply rail; a dead short or open points to a decoupling capacitor or the chip itself.
- Power up and check pin 20 sits at 4.75 to 5.25 V. A sagging rail can make a 3-state output float when it should drive, which on a bus looks like a stuck line.
- Drive an A input and toggle the corresponding G enable: with G low, the Y output must follow A; with G high, Y must be high impedance (read with a pull-up and a pull-down in turn).
- If a bus line is stuck high or low, lift the 74LS244 enable and check whether the stuck level follows the chip or stays on the bus — a stuck bus points to another driver, a stuck chip points here.
- Scope the enable pins during bus cycles; a slow edge on G can let two drivers fight for a few nanoseconds, which is enough to glitch the bus and corrupt a memory read.