Pinout diagram
Used in Retro Machine Hubs
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Summary specifications
Technology
NMOS
Operating Voltage
+5 V +/-5% (VCC pin 17, VSS pin 1)
Clock
3.579545 MHz NTSC colourburst clock input on Pin 33 (CLK)
Text Mode
32 x 16 characters (internal 5x7 uppercase + inverse/semigraphics ROM)
Graphics Modes
64x64, 128x64, 128x96, 128x192, and 256x192 (selected via A/G and GM0-GM2 pins)
Video Outputs
Analog Y (Pin 28), R-Y / phiA (Pin 11), B-Y / phiB (Pin 10), CHB Reference (Pin 9)
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | VSS | Ground | Power | 0 V | System ground (0 V). |
| 2 | DD6 | Data Bus | Input | TTL | Display Data input bit 6 (often tied to INV Pin 32 for inverse characters). |
| 3 | DD0 | Data Bus | Input | TTL | Display Data input bit 0 (LSB). |
| 4 | DD1 | Data Bus | Input | TTL | Display Data input bit 1. |
| 5 | DD2 | Data Bus | Input | TTL | Display Data input bit 2. |
| 6 | DD3 | Data Bus | Input | TTL | Display Data input bit 3. |
| 7 | DD4 | Data Bus | Input | TTL | Display Data input bit 4. |
| 8 | DD5 | Data Bus | Input | TTL | Display Data input bit 5. |
| 9 | CHB | Analog | Output | Analog ref | Chroma Bias reference (~1.5 V DC reference for LM1889/MC1372). |
| 10 | phiB (B-Y) | Analog | Output | Analog video | Blue colour-difference (B-Y / Pb) output. |
| 11 | phiA (R-Y) | Analog | Output | Analog video | Red colour-difference (R-Y / Pr) output. |
| 12 | /MS | Control | Input | TTL, active low | Memory Select. Low tri-states the VDG's DA0-DA12 address outputs (tied low when paired with an MC6883 SAM). |
| 13 | DA5 | Address Bus | Tri-state output | TTL | Display Address output bit 5. |
| 14 | DA6 | Address Bus | Tri-state output | TTL | Display Address output bit 6. |
| 15 | DA7 | Address Bus | Tri-state output | TTL | Display Address output bit 7. |
| 16 | DA8 | Address Bus | Tri-state output | TTL | Display Address output bit 8. |
| 17 | VCC | Power | Power | +5 V | +5 V main supply. |
| 18 | DA9 | Address Bus | Tri-state output | TTL | Display Address output bit 9. |
| 19 | DA10 | Address Bus | Tri-state output | TTL | Display Address output bit 10. |
| 20 | DA11 | Address Bus | Tri-state output | TTL | Display Address output bit 11. |
| 21 | DA12 | Address Bus | Tri-state output | TTL | Display Address output bit 12 (6 KB max direct address range). |
| 22 | DA0 | Address Bus | Tri-state output | TTL | Display Address output bit 0 (feeds MC6883 SAM synchronization on Dragon/CoCo). |
| 23 | DA1 | Address Bus | Tri-state output | TTL | Display Address output bit 1. |
| 24 | DA2 | Address Bus | Tri-state output | TTL | Display Address output bit 2. |
| 25 | DA3 | Address Bus | Tri-state output | TTL | Display Address output bit 3. |
| 26 | DA4 | Address Bus | Tri-state output | TTL | Display Address output bit 4. |
| 27 | GM2 | Control | Input | TTL | Graphics Mode select bit 2 (driven by 6821 PIA2 on Dragon/CoCo, or 8255 on Acorn Atom). |
| 28 | Y | Analog | Output | Analog luma+sync | Composite Luminance + Sync output. |
| 29 | GM1 | Control | Input | TTL | Graphics Mode select bit 1. |
| 30 | GM0 | Control | Input | TTL | Graphics Mode select bit 0. |
| 31 | /INT/EXT | Control | Input | TTL | Internal/External character ROM select. |
| 32 | INV | Control | Input | TTL | Inverse video character control (swaps black and green/orange text). |
| 33 | CLK | Clock / Timing | Input | TTL 3.58 MHz | 3.579545 MHz video dot clock input. |
| 34 | /A/S | Control | Input | TTL | Alphanumeric / Semigraphics select (usually tied to DD7 Bit 7 of display RAM!). |
| 35 | /A/G | Control | Input | TTL | Alphanumeric (0) / Bitmap Graphics (1) mode select. |
| 36 | /RP | Control | Output | TTL, active low | Row Preset output pulse. |
| 37 | /FS | Control | Output | TTL, active low | Field Sync (Vertical Blanking) output — feeds PIA1 50/60 Hz VSYNC interrupt and MC6883 SAM counter reset! |
| 38 | /HS | Control | Output | TTL, active low | Horizontal Sync (15.7 kHz) output — feeds PIA1 HSYNC input and MC6883 SAM row advance! |
| 39 | CSS | Control | Input | TTL | Colour Set Select (0 = Green/Yellow/Blue/Red set, 1 = Buff/Cyan/Magenta/Orange set). |
| 40 | DD7 | Data Bus | Input | TTL | Display Data input bit 7 (MSB). |
Common uses and repair diagnostics
The Motorola MC6847 Video Display Generator (VDG) is a 40-pin NMOS display chip that reads display memory and generates 32x16 text (using an internal 64-character uppercase mask ROM), semigraphics, and up to 256x192 bitmap graphics in a 9-colour palette. Rather than outputting composite video directly, the MC6847 outputs three analogue colour-difference signals — Pin 28 (Y Luminance + Sync), Pin 11 (phiA / R-Y), and Pin 10 (phiB / B-Y) — which feed an external LM1889 / MC1372 colour modulator.
Used in the Dragon 32 and Dragon 64, Tandy TRS-80 Color Computer (CoCo 1 and CoCo 2), Acorn Atom, Laser 200 / VZ200, and NEC PC-6001. On the Dragon and CoCo, the MC6847's /HS (Pin 38), /FS (Pin 37), and DA0 (Pin 22) pins synchronize the MC6883 SAM's internal video address counter.
- Scope Pin 33 (CLK) for 3.58 MHz, Pin 38 (/HS) for 15.7 kHz pulses, and Pin 37 (/FS) for 50/60 Hz vertical sync pulses.
- Check Pin 28 (Y): if valid luma+sync is present on Pin 28 of the MC6847, any black-screen or no-colour symptom downstream lies in the LM1889 / MC1372 modulator or video buffer transistor.
- Note that in text mode, ASCII space ($20) is stored in RAM as $60 (0110 0000) so INV (DD6) is high (black characters on green background)!