Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | A11 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 11. Tri-state during a bus acknowledge. |
| 2 | A12 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 12. |
| 3 | A13 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 13. |
| 4 | A14 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 14. |
| 5 | A15 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 15, the most significant address line. |
| 6 | CLK | Clock / Timing | Input | TTL clock | Single-phase clock input. All bus timing is derived from this pin. |
| 7 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 4. |
| 8 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 5. |
| 9 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 3. |
| 10 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 6. |
| 11 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. |
| 12 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 2. |
| 13 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 7, the most significant data line. |
| 14 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 0. |
| 15 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 1. |
| 16 | /INT | Control | Input | TTL, active low | Active low. Maskable interrupt request. Serviced at the end of the current instruction if interrupts are enabled. |
| 17 | /NMI | Control | Input | TTL, active low | Active low. Non-maskable interrupt. Always serviced; jumps to 0066H. |
| 18 | /HALT | Control | Output | TTL, active low | Active low. Halt state. Low while the CPU executes a HALT instruction and waits for an interrupt. |
| 19 | /MREQ | Control | Output | TTL, active low | Active low. Memory request. Low when the address bus holds a valid memory address. |
| 20 | /IORQ | Control | Output | TTL, active low | Active low. I/O request. Low when the address bus holds a valid I/O port address. |
| 21 | /RD | Control | Output | TTL, active low | Active low. Read strobe. Low when the CPU wants to read data from memory or an I/O port. |
| 22 | /WR | Control | Output | TTL, active low | Active low. Write strobe. Low when the CPU is writing data to memory or an I/O port. |
| 23 | /BUSACK | Control | Output | TTL, active low | Active low. Bus acknowledge. Low to signal that the CPU has released the bus to an external master. |
| 24 | /WAIT | Control | Input | TTL, active low | Active low. Wait request. Held low by slow memory or I/O to stretch the current bus cycle. |
| 25 | /BUSREQ | Control | Input | TTL, active low | Active low. Bus request. Held low by a DMA controller to ask the CPU to release the buses. |
| 26 | /RESET | Control | Input | TTL, active low | Active low. Reset. Low for at least three clock cycles to reset the CPU and clear PC, I and R. |
| 27 | /M1 | Control | Output | TTL, active low | Active low. Machine cycle one. Low during the opcode fetch; also used with IORQ for an interrupt acknowledge. |
| 28 | /RFSH | Control | Output | TTL, active low | Active low. Refresh. Low during a refresh cycle; the low address bits hold the refresh counter. |
| 29 | GND | Ground | Power | 0 V | Ground reference. |
| 30 | A0 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 0. |
| 31 | A1 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 1. |
| 32 | A2 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 2. |
| 33 | A3 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 3. |
| 34 | A4 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 4. |
| 35 | A5 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 5. |
| 36 | A6 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 6. |
| 37 | A7 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 7. |
| 38 | A8 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 8. |
| 39 | A9 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 9. |
| 40 | A10 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 10. |
Common uses and repair diagnostics
The Zilog Z80 is the 8-bit CPU that powered the ZX Spectrum, the MSX, the Amstrad CPC and a generation of CP/M machines. It presents a 16-bit address bus, an 8-bit bidirectional data bus and a refresh output that made dynamic RAM cheap to use, and it is still produced today in CMOS form as the Z84C00.
The Z80 sits at the centre of the ZX Spectrum, the MSX, the Amstrad CPC and most CP/M business machines. Its 16-bit address bus decodes straight into 64 KB of memory, its refresh output drives dynamic RAM without extra logic, and its two interrupt inputs let a peripheral force a restart (NMI) or supply a vector (INT) — the basis of the Spectrum's ZX Interface 1 and the MSX's slot expansions.
On the bench a dead Z80 usually shows up as a black screen with no address activity. Probe CLK (pin 6) first: no clock means the crystal or oscillator has failed, not the CPU. If the clock is good but the address bus is stuck, lift the CPU and check the board; a shorted data or control line elsewhere will hold the Z80 in a permanent wait. The CMOS Z84C00 is a drop-in for the NMOS Z08400 and runs cooler, so it is the usual replacement when an original part runs too hot.
- Scope pin 6 (CLK) for a clean clock at the rated speed. No clock is the most common cause of a dead Z80 board and is not the CPU's fault.
- Check pin 11 (VCC) at 5 V and pin 29 (GND) at 0 V; a sagging supply stalls the CPU before anything else fails.
- Probe the address bus (pins 1 to 5 and 30 to 40) during reset. A bus that never toggles suggests a stuck line or a shorted peripheral holding the bus.
- Hold pin 26 (RESET) low for three clocks, then release; the CPU should fetch from address 0000H, driving M1 (pin 27) low and MREQ (pin 19) low.
- If WAIT (pin 24) is stuck low, the CPU will never finish a cycle. Lift WAIT and see if the board wakes — a faulty memory chip often holds this line.