Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | NC | No Connect | Not connected | No connect | No connect. |
| 2 | COLOR | Analog | Output | Analogue composite | Composite colour output. Carries the chroma signal to the RF modulator or video connector. |
| 3 | S/LUM | Analog | Output | Analogue composite | Separate luma output. The brightness signal; combined with COLOR for composite video. |
| 4 | R/W | Control | Input | TTL | Read / Write. High reads a register, low writes one. |
| 5 | D11 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 11. D8 to D11 (pins 5-8) are the extra 4 bits used for colour. The whole 12-bit bus runs D11 down to D0 across pins 5 to 16. |
| 6 | D10 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 10. |
| 7 | D9 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 9. |
| 8 | D8 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 8. |
| 9 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 7. The main data bus D7-D0 runs down pins 9 to 16, directly below the colour bits. |
| 10 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 6. |
| 11 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 5. |
| 12 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 4. |
| 13 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 3. |
| 14 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 2. |
| 15 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 1. |
| 16 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 0. |
| 17 | POTX | Analog | Input | Analogue paddle | Paddle X input. An RC charge time on this pin is digitised to read a potentiometer. |
| 18 | POTY | Analog | Input | Analogue paddle | Paddle Y input. Same RC ADC as POTX for the second axis. |
| 19 | AUDIO | Analog | Output | Analogue audio | Audio output. Three tone oscillators, a noise generator and an amplitude modulator all come out here. On a VIC-20, loss of both picture and sound points at this chip. |
| 20 | VSS | Ground | Power | 0 V | Ground. One of two supply pins: VSS (20) and VDD (40). Single +5 V part. |
| 21 | A0 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 0. The address bus is a plain, non-multiplexed A0-A13 on pins 21-34 — easier to probe than the VIC-II multiplexed bus. |
| 22 | A1 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 1. |
| 23 | A2 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 2. |
| 24 | A3 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 3. |
| 25 | A4 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 4. |
| 26 | A5 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 5. |
| 27 | A6 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 6. |
| 28 | A7 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 7. |
| 29 | A8 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 8. |
| 30 | A9 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 9. |
| 31 | A10 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 10. |
| 32 | A11 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 11. |
| 33 | A12 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 12. |
| 34 | A13 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 13, the most significant address line. |
| 35 | PPHI1 | Clock / Timing | Output | TTL clock | Processor phase 1 clock output. One of two processor clock outputs derived from the video timing. |
| 36 | PPHI2 | Clock / Timing | Output | TTL clock | Processor phase 2 clock output. The main CPU clock for the VIC-20 system. |
| 37 | OPTION | Control | Input | TTL | Option input. Selects interlaced or non-interlaced scan mode. |
| 38 | PHI2 | Clock / Timing | Input | TTL clock | Phase 2 clock input. One of two clock inputs that drive the video timing. |
| 39 | PHI1 | Clock / Timing | Input | TTL clock | Phase 1 clock input. Works with PHI2 to clock the video timing. |
| 40 | VDD | Power | Power | +5 V | Positive supply. Single +5 V part, which makes it much less troublesome than the 12 V VIC-II. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The MOS 6560 is the video and sound chip of the Commodore VIC-20 — the VIC the machine is named after. Unlike the later VIC-II it also contains the sound system: three tone oscillators, a noise generator and an amplitude modulator, all on AUDIO (pin 19). So on a VIC-20 a loss of both picture and sound points at one chip. The 6560 is NTSC; the 6561 is PAL-B.
The 6560 is the VIC-20 video and sound chip — the VIC the machine is named after. Unlike the VIC-II it also contains the sound system: three tone oscillators, a noise generator and an amplitude modulator, all on AUDIO (pin 19). So on a VIC-20 a loss of both picture and sound points at one chip. It also has the two 8-bit A/D converters for the paddles on POTX and POTY (pins 17 and 18).
The 12-bit data bus runs D11 down to D0 across pins 5 to 16: D8 to D11 (pins 5-8) are the extra 4 bits for colour, sitting directly above the main data bus D7 to D0 (pins 9-16). The address bus is a plain, non-multiplexed A0-A13 on pins 21-34, easier to probe than the VIC-II multiplexed bus. The 6560 is NTSC; the 6561 is PAL-B. Only two supply pins (VSS 20, VDD 40) and a single +5 V rail make it much less troublesome than the 12 V VIC-II.
- Check pin 40 (VDD) at 5 V and pin 20 (VSS) at 0 V. Single +5 V supply — much simpler than the VIC-II.
- Loss of both picture and sound points at the 6560, since it contains the sound system too. Probe pin 19 (AUDIO) for activity.
- No picture only: probe the colour (pin 2) and luma (pin 3) outputs, and check the clock inputs (PHI1 pin 39, PHI2 pin 38).
- The address bus (pins 21-34) is non-multiplexed, so a logic probe should show clean A0-A13 activity — easier to read than the VIC-II.
- Paddle inputs not working: check POTX (pin 17) and POTY (pin 18) for the RC charge waveform.