Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | PA3 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 3. Port A is split across the package and descends: PA3 down to PA0 on pins 1-4, and PA7 down to PA4 on pins 37-40. Two ports, two completely different conventions. |
| 2 | PA2 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 2. |
| 3 | PA1 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 1. |
| 4 | PA0 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 0. |
| 5 | /RD | Control | Input | TTL, active low | Active low. Read strobe. Low reads the selected port or register onto the data bus. |
| 6 | /CS | Control | Input | TTL, active low | Active low. Chip select. Low enables the data bus for register access. |
| 7 | GND | Ground | Power | 0 V | Ground. Power is at pin 7 (GND) and pin 26 (VCC) — neither at a corner. |
| 8 | A1 | Address Bus | Input | TTL | Address bit 1. A0 (pin 9) and A1 select one of four registers: port A, port B, port C and the control word. Note A1 is on the LOWER pin number (8) and A0 on 9. |
| 9 | A0 | Address Bus | Input | TTL | Address bit 0. |
| 10 | PC7 | I/O | Bidirectional | TTL, 0 V / 5 V | Port C bit 7. The upper nibble DESCENDS: PC7, PC6, PC5, PC4 on pins 10, 11, 12, 13. The lower nibble then ASCENDS: PC0, PC1, PC2, PC3 on pins 14, 15, 16, 17. The sequence across pins 10 to 17 is 7, 6, 5, 4, 0, 1, 2, 3. Nothing else in this library does that — it is the single most common 8255 wiring error. |
| 11 | PC6 | I/O | Bidirectional | TTL, 0 V / 5 V | Port C bit 6. |
| 12 | PC5 | I/O | Bidirectional | TTL, 0 V / 5 V | Port C bit 5. |
| 13 | PC4 | I/O | Bidirectional | TTL, 0 V / 5 V | Port C bit 4. |
| 14 | PC0 | I/O | Bidirectional | TTL, 0 V / 5 V | Port C bit 0. The lower nibble ASCENDS: PC0, PC1, PC2, PC3 on pins 14, 15, 16, 17 — the opposite direction from the upper nibble on pins 10-13. |
| 15 | PC1 | I/O | Bidirectional | TTL, 0 V / 5 V | Port C bit 1. |
| 16 | PC2 | I/O | Bidirectional | TTL, 0 V / 5 V | Port C bit 2. |
| 17 | PC3 | I/O | Bidirectional | TTL, 0 V / 5 V | Port C bit 3. |
| 18 | PB0 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 0. Port B is a clean ascending run of PB0 to PB7 on pins 18-25 — unlike port A, which is split and descends. |
| 19 | PB1 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 1. |
| 20 | PB2 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 2. |
| 21 | PB3 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 3. |
| 22 | PB4 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 4. |
| 23 | PB5 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 5. |
| 24 | PB6 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 6. |
| 25 | PB7 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 7. |
| 26 | VCC | Power | Power | +5 V | Positive supply. Power is at pin 7 (GND) and pin 26 (VCC) — neither at a corner. Decouple with 100 nF close to the pin. |
| 27 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 7. The data bus descends D7 (pin 27) to D0 (pin 34). |
| 28 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 6. |
| 29 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 5. |
| 30 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 4. |
| 31 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 3. |
| 32 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 2. |
| 33 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 1. |
| 34 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 0. |
| 35 | RESET | Control | Input | TTL, active high | Reset. ACTIVE HIGH — almost everything else of this era is active low. No slash. Must be pulsed high at power-up or all three ports stay in input mode, which presents as "the outputs do nothing". |
| 36 | /WR | Control | Input | TTL, active low | Active low. Write strobe. Low writes the data bus to the selected port or register. |
| 37 | PA7 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 7. The top half of port A descends: PA7, PA6, PA5, PA4 on pins 37-40. |
| 38 | PA6 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 6. |
| 39 | PA5 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 5. |
| 40 | PA4 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 4. |
Common uses and repair diagnostics
The Intel 8255A PPI (Programmable Peripheral Interface) gives a CPU three 8-bit I/O ports in one 40-pin DIP. Three separate layout traps make this page worth reading carefully: port C's two nibbles run in OPPOSITE directions, port A is split across the package and descends, and RESET on pin 35 is ACTIVE HIGH — almost everything else of this era is active low. Power is at pin 7 (GND) and pin 26 (VCC), neither at a corner.
The Intel 8255A PPI gives a CPU three 8-bit I/O ports in one 40-pin DIP. Three separate layout traps make this chip the easiest in the library to wire wrong: - Port C's two nibbles run in OPPOSITE directions. The upper nibble DESCENDS: PC7, PC6, PC5, PC4 on pins 10, 11, 12, 13. The lower nibble then ASCENDS: PC0, PC1, PC2, PC3 on pins 14, 15, 16, 17. The sequence across pins 10 to 17 is 7, 6, 5, 4, 0, 1, 2, 3. Nothing else in this library does that. It is the single most common 8255 wiring error. - Port A is split across the package and descends. PA3 down to PA0 on pins 1-4, and PA7 down to PA4 on pins 37-40. Port B, by contrast, is a clean ascending run of PB0 to PB7 on pins 18-25. Two ports, two completely different conventions. - RESET on pin 35 is ACTIVE HIGH. Almost everything else of this era is active low. No slash on it. It must be pulsed high at power-up or all three ports stay in input mode, which presents as "the outputs do nothing".
Power is at pin 7 (GND) and pin 26 (VCC) — neither at a corner. Data bus descends D7 (pin 27) to D0 (pin 34). Only A0 (pin 9) and A1 (pin 8) for addressing — four registers: port A, port B, port C and the control word. Note A1 is on the LOWER pin number.
Mode 0 is simple latched I/O; mode 1 adds handshaking using port C bits as strobes and acknowledgements; mode 2 makes port A a bidirectional bus. In modes 1 and 2 you lose port C bits to handshaking, which surprises people who wanted 24 free I/O. Port C supports bit set/reset through the control word, so individual bits can be toggled without a read-modify-write.
Used in the MSX (joystick, keyboard and slot select), the Amstrad CPC (keyboard, AY-3-8910 interface and tape), the IBM PC XT (keyboard, DIP switches, speaker gate), and a huge amount of arcade and industrial hardware. On a CPC the 8255 sits between the CPU and the sound chip, so "no sound AND no keyboard" points here rather than at the AY.
- Write the control word for all-outputs, then walk a single high bit along each port and confirm it appears on the right pin. Check port C carefully — the nibbles run in opposite directions.
- Check RESET (pin 35) is not stuck high, which holds every port in input mode permanently — presents as "the outputs do nothing".
- Remember RESET is ACTIVE HIGH. A stuck-low /RESET is not a fault on this chip; a stuck-high RESET is.
- On a CPC, "no sound AND no keyboard" points at the 8255 (which sits between the CPU and the AY), not at the sound chip.
- Port A is split: PA3-PA0 on pins 1-4, PA7-PA4 on pins 37-40. Do not assume it is contiguous.