Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | 1A | I/O | Input | CMOS Schmitt, 0 V / VDD | Gate 1, input A. Schmitt-trigger: rising threshold approx. 2.3 V, falling threshold approx. 1.5 V at 5 V. CMOS inputs are high impedance; never leave unused inputs floating. |
| 2 | 1B | I/O | Input | CMOS Schmitt, 0 V / VDD | Gate 1, input B. Schmitt-trigger thresholds as pin 1. |
| 3 | 1Y | I/O | Output | CMOS push-pull | Gate 1 output. Low only when both 1A and 1B are above the rising threshold. |
| 4 | 2Y | I/O | Output | CMOS push-pull | Gate 2 output. Low only when both 2A and 2B are above the rising threshold. |
| 5 | 2A | I/O | Input | CMOS Schmitt, 0 V / VDD | Gate 2, input A. Schmitt-trigger thresholds as pin 1. |
| 6 | 2B | I/O | Input | CMOS Schmitt, 0 V / VDD | Gate 2, input B. Schmitt-trigger thresholds as pin 1. |
| 7 | VSS | Ground | Power | 0 V | Negative supply (ground return for all four gates). |
| 8 | 3A | I/O | Input | CMOS Schmitt, 0 V / VDD | Gate 3, input A. Schmitt-trigger thresholds as pin 1. |
| 9 | 3B | I/O | Input | CMOS Schmitt, 0 V / VDD | Gate 3, input B. Schmitt-trigger thresholds as pin 1. |
| 10 | 3Y | I/O | Output | CMOS push-pull | Gate 3 output. Low only when both 3A and 3B are above the rising threshold. |
| 11 | 4Y | I/O | Output | CMOS push-pull | Gate 4 output. Low only when both 4A and 4B are above the rising threshold. |
| 12 | 4A | I/O | Input | CMOS Schmitt, 0 V / VDD | Gate 4, input A. Schmitt-trigger thresholds as pin 1. |
| 13 | 4B | I/O | Input | CMOS Schmitt, 0 V / VDD | Gate 4, input B. Schmitt-trigger thresholds as pin 1. |
| 14 | VDD | Power | Power | +3 V to +15 V | Positive supply. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The CD4093 is the 4000-series quad 2-input NAND gate with Schmitt-trigger inputs. It shares the CD4011 pinout exactly — outputs on pins 3, 4, 10 and 11, VSS on 7, VDD on 14 — but the inputs have hysteresis, so a slow or noisy input edge produces a single clean output transition instead of a burst of oscillation. A plain CD4011 input switches at a single threshold, so a signal that lingers around that threshold makes the output chatter; a CD4093 input has separate rising and falling thresholds, so the same signal produces one clean edge. It is the CMOS counterpart of the 74LS14, and the two share the same use case: debounce, signal conditioning and simple RC oscillators.
The CD4093 is the part you reach for whenever a CMOS board needs a NAND gate on a slow or noisy input edge. It builds the simple RC oscillators that some retro boards use for their clocks, the debounce circuits that clean up mechanical switch inputs, and the signal-conditioning stages that turn a messy sensor output into a clean logic edge. A plain CD4011 would chatter on those edges; the Schmitt hysteresis on the CD4093 turns each messy transition into one clean output edge. The NAND function means a single gate can combine two conditions and clean the result at the same time, which is why the part is so common in low-power timing and control circuits.
The CD4093 shares its pinout with the CD4011, so the two are physically interchangeable — but the CD4011 has no hysteresis, so dropping a CD4011 into a CD4093 socket on a slow-edge circuit makes the output chatter. The 74LS14 is the TTL counterpart with the same Schmitt-trigger behaviour but the hex-inverter pinout (six single-input gates, not four 2-input gates).
- Confirm pin 14 (VDD) is within 3 to 15 V and pin 7 (VSS) is at 0 V. Overvoltage or reversed rails kill CMOS instantly.
- Drive both inputs of a gate above the rising threshold and check the output goes low; drive both below the falling threshold and check it goes high. A stuck level suggests a dead gate.
- Drive an input with a slow ramp and watch the output switch once, cleanly. Multiple transitions mean the Schmitt thresholds have drifted or the input is too noisy even for the hysteresis.
- Tie every unused input — on a used gate or a spare one — to VSS or VDD. A floating CMOS input drifts and, on a Schmitt part, can sit between the thresholds and draw extra current.
- If the chip runs warm, suspect a floating input or an output shorted to another gate — CMOS should draw microamps at rest.