Pinout diagram
Used in Retro Machine Hubs
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Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | DRD6 | Data Bus | Bidirectional | TTL | Chip RAM Data bus bit 6. |
| 2 | DRD5 | Data Bus | Bidirectional | TTL | Chip RAM Data bus bit 5. |
| 3 | DRD4 | Data Bus | Bidirectional | TTL | Chip RAM Data bus bit 4. |
| 4 | DRD3 | Data Bus | Bidirectional | TTL | Chip RAM Data bus bit 3. |
| 5 | DRD2 | Data Bus | Bidirectional | TTL | Chip RAM Data bus bit 2. |
| 6 | DRD1 | Data Bus | Bidirectional | TTL | Chip RAM Data bus bit 1. |
| 7 | DRD0 | Data Bus | Bidirectional | TTL | Chip RAM Data bus bit 0 (LSB). |
| 8 | VSS1 | Ground | Power | 0 V | Digital ground. |
| 9 | RGA8 | Address Bus | Input | TTL | Register Address Bus bit 8 from Agnus. |
| 10 | RGA7 | Address Bus | Input | TTL | Register Address Bus bit 7. |
| 11 | RGA6 | Address Bus | Input | TTL | Register Address Bus bit 6. |
| 12 | RGA5 | Address Bus | Input | TTL | Register Address Bus bit 5. |
| 13 | RGA4 | Address Bus | Input | TTL | Register Address Bus bit 4. |
| 14 | RGA3 | Address Bus | Input | TTL | Register Address Bus bit 3. |
| 15 | RGA2 | Address Bus | Input | TTL | Register Address Bus bit 2. |
| 16 | RGA1 | Address Bus | Input | TTL | Register Address Bus bit 1 (LSB). |
| 17 | /RST | Control | Input | TTL, active low | System Reset input. |
| 18 | DMAL | Control | Output | TTL | DMA Request Line serial stream out to Agnus Pin 61 (requests audio and floppy DMA transfers). |
| 19 | VCC (+5V) | Power | Power | +5 V | Main +5 V digital supply. |
| 20 | CCKQ | Clock / Timing | Input | TTL 3.55 MHz | Colour Clock Quadrature input from Agnus. |
| 21 | /IPL0 | Control | Output | TTL, active low | Interrupt Priority Level 0 output to 68000 Pin 25. |
| 22 | /IPL1 | Control | Output | TTL, active low | Interrupt Priority Level 1 output to 68000 Pin 24. |
| 23 | /IPL2 | Control | Output | TTL, active low | Interrupt Priority Level 2 output to 68000 Pin 23. |
| 24 | /INT2 | Control | Input | TTL, active low | External Interrupt Level 2 input (from CIA-A, Zorro slots, and Gayle IDE). |
| 25 | /INT3 | Control | Input | TTL, active low | External Interrupt Level 3 input. |
| 26 | /INT6 | Control | Input | TTL, active low | External Interrupt Level 6 input (from CIA-B and Zorro slots). |
| 27 | VSS2 | Ground | Power | 0 V | Digital ground. |
| 28 | CCK | Clock / Timing | Input | TTL 3.55 MHz | Master 3.55 MHz Colour Clock input from Agnus. |
| 29 | AVSS (AGND) | Ground | Power | 0 V Analog | Analog Audio Ground. |
| 30 | RIGHT | Analog | Output | Analog audio | Right Stereo Audio output (Channels 1 & 2) to external LF347 / TL084 op-amp filter. |
| 31 | LEFT | Analog | Output | Analog audio | Left Stereo Audio output (Channels 0 & 3) to external LF347 / TL084 op-amp filter. |
| 32 | POT0X | Analog | Bidirectional | Analog/TTL | Mouse/Joystick Port 1 Pot X (Middle Mouse Button on DB9 Pin 5!). |
| 33 | POT0Y | Analog | Bidirectional | Analog/TTL | Mouse/Joystick Port 1 Pot Y (RIGHT MOUSE BUTTON on DB9 Pin 9!). If Right Mouse Button fails, check Pin 33! |
| 34 | AVDD (AREF) | Power | Power | +5 V Analog | Analog +5 V reference supply. |
| 35 | POT1X | Analog | Bidirectional | Analog/TTL | Joystick Port 2 Pot X (DB9 Pin 5). |
| 36 | POT1Y | Analog | Bidirectional | Analog/TTL | Joystick Port 2 Pot Y (DB9 Pin 9 — Joystick 2 Fire Button 2). |
| 37 | /DKRD | I/O | Input | TTL, active low | Floppy Disk Read Data MFM pulse input (from Pin 30 of internal/external floppy connector). |
| 38 | /DKWD | I/O | Output | TTL, active low | Floppy Disk Write Data MFM pulse output. |
| 39 | DKWE | Control | Output | TTL | Floppy Disk Write Enable gate output. |
| 40 | TXD | I/O | Output | TTL | RS-232 Serial Transmit Data output (to 1488 line driver). |
| 41 | RXD | I/O | Input | TTL | RS-232 Serial Receive Data input (from 1489 line receiver). |
| 42 | DRD15 | Data Bus | Bidirectional | TTL | Chip RAM Data bus bit 15 (MSB). |
| 43 | DRD14 | Data Bus | Bidirectional | TTL | Chip RAM Data bus bit 14. |
| 44 | DRD13 | Data Bus | Bidirectional | TTL | Chip RAM Data bus bit 13. |
| 45 | DRD12 | Data Bus | Bidirectional | TTL | Chip RAM Data bus bit 12. |
| 46 | DRD11 | Data Bus | Bidirectional | TTL | Chip RAM Data bus bit 11. |
| 47 | DRD10 | Data Bus | Bidirectional | TTL | Chip RAM Data bus bit 10. |
| 48 | DRD9 / 8 / 7 | Data Bus | Bidirectional | TTL | Chip RAM Data bus bit 7/8/9. |
Common uses and repair diagnostics
Named after 'Ports, Audio, UART and Logic', Glenn Keller's 48-pin MOS 8364 Paula was so ahead of its time in 1985 that Commodore kept the exact same chip unchanged across every single OCS, ECS, and AGA Amiga ever built (from the A1000 and A500 to the A1200 and A4000)! Paula houses: (1) four independent 8-bit PCM DMA audio channels (2 routed to Pin 31 LEFT, 2 routed to Pin 30 RIGHT, with 6-bit volume DACs), (2) the Amiga's MFM/GCR floppy disk DMA read/write serializer (DKRD, DKWD, DKWE), (3) the master 68000 interrupt priority encoder (/IPL0-/IPL2 on Pins 21-23), (4) the full-duplex RS-232 serial port UART (TXD/RXD), and (5) four analogue proportional/paddle RC inputs (POT0X/Y, POT1X/Y — which also read the Right and Middle Mouse Buttons!).
Used in every classic Amiga: A1000, A500, A500+, A2000, A3000 (DIP-48), and A600, A1200, A4000, CD32 (PLCC-52 surface-mount package).
- Right Mouse Button stuck or not opening the Amiga Workbench menu bar: the Right Mouse Button connects to Paula Pin 33 (POT0Y) via EMI filter resistor/cap! Check continuity from DB9 Pin 9 to Paula Pin 33 before replacing Paula.
- Distorted, quiet, or missing audio on one stereo channel: scope Paula Pin 30 (RIGHT) and Pin 31 (LEFT) directly. In 95% of cases, Paula's audio output is clean and the fault is leaky 22 uF coupling capacitors or a missing -12 V rail on the external LF347 / TL084 op-amp!