Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | VSS | Ground | Power | 0 V | Ground. Note: VCC is pin 20, NOT pin 40. Pin 40 is CA1, an input — 5 V here will damage the chip. |
| 2 | PA0 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 0. Independently programmable as input or output. |
| 3 | PA1 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 1. |
| 4 | PA2 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 2. |
| 5 | PA3 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 3. |
| 6 | PA4 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 4. |
| 7 | PA5 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 5. |
| 8 | PA6 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 6. |
| 9 | PA7 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 7. |
| 10 | PB0 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 0. Independently programmable as input or output. |
| 11 | PB1 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 1. |
| 12 | PB2 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 2. |
| 13 | PB3 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 3. |
| 14 | PB4 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 4. |
| 15 | PB5 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 5. |
| 16 | PB6 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 6. Can be controlled by Timer 1 in square-wave mode. |
| 17 | PB7 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 7. Can be controlled by Timer 1; also used as a pulse count input for Timer 2. |
| 18 | CB1 | I/O | Bidirectional | TTL | Port B control line 1. Interrupt input or handshake input; also the shift-register clock. |
| 19 | CB2 | I/O | Bidirectional | TTL | Port B control line 2. Bidirectional handshake or pulse output; also the shift-register data line. |
| 20 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. This is pin 20, not pin 40. |
| 21 | /IRQ | Control | Open-drain / open-collector | TTL, active low, open drain | Active low. Interrupt request, open-drain. Several VIAs can share one interrupt line with a single pull-up. A shorted /IRQ holds the whole system in an interrupt loop. |
| 22 | R/W | Control | Input | TTL | Read / Write. High reads a register, low writes one. |
| 23 | /CS2 | Control | Input | TTL, active low | Active low. Chip select 2. Both CS1 (pin 24) high AND /CS2 low must be satisfied for the register file to respond. |
| 24 | CS1 | Control | Input | TTL | Chip select 1, active HIGH. Both CS1 high AND /CS2 (pin 23) low must be satisfied. Note the opposite polarity of the two selects. |
| 25 | PHI2 | Clock / Timing | Input | TTL clock | Phase 2 system clock. All register access is timed to this clock. |
| 26 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 7. |
| 27 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 6. |
| 28 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 5. |
| 29 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 4. |
| 30 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 3. |
| 31 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 2. |
| 32 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 1. |
| 33 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 0. |
| 34 | /RES | Control | Input | TTL, active low | Active low. Reset. Clears all registers and sets all port lines to input. |
| 35 | RS3 | Address Bus | Input | TTL | Register select bit 3. RS0 to RS3 select one of 16 register addresses. |
| 36 | RS2 | Address Bus | Input | TTL | Register select bit 2. |
| 37 | RS1 | Address Bus | Input | TTL | Register select bit 1. |
| 38 | RS0 | Address Bus | Input | TTL | Register select bit 0. |
| 39 | CA2 | I/O | Bidirectional | TTL | Port A control line 2. Bidirectional handshake or pulse output. |
| 40 | CA1 | I/O | Input | TTL | Port A control line 1. INPUT ONLY — unlike CA2, CB1 and CB2, this pin cannot be an output. Do not put 5 V here; it is not VCC. |
Common uses and repair diagnostics
The MOS 6522 Versatile Interface Adapter gives a 6502-family CPU two 8-bit bidirectional ports, two 16-bit timers and an 8-bit shift register. It is the standard peripheral chip of the 6502 world, and it turns up in pairs in the VIC-20 and the Commodore 1541 disk drive. Note the supply pins: VSS is pin 1 and VCC is pin 20 — NOT pin 40. Pin 40 is CA1, an input; putting 5 V on it will damage the chip.
The 6522 VIA is the standard peripheral chip of the 6502 world. It turns up in pairs in the VIC-20 (one system VIA, one user VIA) and in the Commodore 1541 disk drive (one for the drive mechanism, one for the serial bus), and on many Apple II peripheral cards and BBC Micro boards. Two 8-bit ports, two 16-bit timers and a shift register cover most glue-logic needs, and the open-drain /IRQ lets several VIAs share one interrupt line.
The supply trap is the headline: VCC is pin 20, not pin 40. Pin 40 is CA1, an input-only control line — putting 5 V on it will damage the chip. The two chip selects have opposite polarity: CS1 (pin 24) is active high, /CS2 (pin 23) is active low, and both must be satisfied. The famous 6522 shift-register erratum was worked around in the 1541 firmware, so the CMOS W65C22 — which fixed the shift-register behaviour — is an unreliable substitute in a 1541, where the firmware and fast-loaders were written around the NMOS part's timing.
- Check pin 1 (VSS) at 0 V and pin 20 (VCC) at 5 V. Do NOT expect VCC at pin 40 — that is CA1, an input.
- A port bit stuck high or low that will not follow its data direction register points at a failed VIA.
- In the 1541, a dead VIA usually kills either the drive motor and stepper (port B) or the serial bus handshake (port A).
- If /IRQ (pin 21) is stuck low, the whole system sits in an interrupt loop. Lift /IRQ to see if the fault is the VIA or elsewhere.
- Probe CA1 (pin 40) and CB1 (pin 18) for activity; remember CA1 is input-only and cannot drive a line.