Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | 1A | I/O | Input | CMOS, 0 V / VDD | Gate 1, input A. CMOS inputs are high impedance; never leave unused inputs floating. |
| 2 | 1B | I/O | Input | CMOS, 0 V / VDD | Gate 1, input B. |
| 3 | 1Y | I/O | Output | CMOS push-pull | Gate 1 output. Low only when both 1A and 1B are high. |
| 4 | 2Y | I/O | Output | CMOS push-pull | Gate 2 output. Low only when both 2A and 2B are high. |
| 5 | 2A | I/O | Input | CMOS, 0 V / VDD | Gate 2, input A. |
| 6 | 2B | I/O | Input | CMOS, 0 V / VDD | Gate 2, input B. |
| 7 | VSS | Ground | Power | 0 V | Negative supply (ground return for all four gates). |
| 8 | 3A | I/O | Input | CMOS, 0 V / VDD | Gate 3, input A. |
| 9 | 3B | I/O | Input | CMOS, 0 V / VDD | Gate 3, input B. |
| 10 | 3Y | I/O | Output | CMOS push-pull | Gate 3 output. Low only when both 3A and 3B are high. |
| 11 | 4Y | I/O | Output | CMOS push-pull | Gate 4 output. Low only when both 4A and 4B are high. |
| 12 | 4A | I/O | Input | CMOS, 0 V / VDD | Gate 4, input A. |
| 13 | 4B | I/O | Input | CMOS, 0 V / VDD | Gate 4, input B. |
| 14 | VDD | Power | Power | +3 V to +15 V | Positive supply. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The CD4001 is the 4000-series CMOS quad 2-input NOR gate, and it is the mirror image of the 74LS02 trap. Both are quad NOR gates in a 14-pin DIP, both share the same supply pins (7 ground, 14 VDD/VCC), but the gate pin assignments are completely different: the 74LS02 puts its outputs on pins 1, 4, 10 and 13 (outputs first), while the CD4001 follows the CD4011 layout with outputs on 3, 4, 10 and 11. The two are the same function in two incompatible footprints — swapping one for the other connects gate outputs to pins the board drives as inputs, and the fight that follows usually takes one chip or the other with it.
The CD4001 does the same NOR-gate jobs as the 74LS02 — active-low decoders, reset logic, cross-coupled NOR latches — but in circuits that run from a battery or a wide, unregulated rail. It turns up in 9 V and 12 V control boards, in CMOS logic retrofits of older discrete designs, and in low-power instruments where a TTL part would waste more current than the rest of the board.
The critical thing to know is that the CD4001 is NOT a drop-in replacement for the 74LS02. Both are quad 2-input NOR gates in a 14-pin DIP, both share the same supply pins, but the gate pin assignments are completely different: the 74LS02 puts outputs on 1, 4, 10 and 13, while the CD4001 (following the CD4011 layout) puts them on 3, 4, 10 and 11. Swapping one for the other without rewiring connects gate outputs to pins the board drives as inputs. Always check which family a board was designed for before substituting.
As with all CMOS, tie every unused input — on a used gate or a spare one — to VSS or VDD. The CD4001 is far slower than LS, so it is the wrong choice for anything above a few MHz.
- Confirm pin 14 (VDD) is within 3 to 15 V and pin 7 (VSS) is at 0 V. Overvoltage or reversed rails kill CMOS instantly.
- Before substituting, confirm the board was designed for a CD4001 and not a 74LS02. The two share a package but put outputs on different pins, and swapping them shorts outputs to driven inputs.
- Check every input, including those of spare gates, is tied to a rail. A floating CMOS input reads as an indeterminate voltage and makes the output chatter.
- Measure the output of a driven gate: a CMOS output swings close to both rails. A level stuck halfway usually means an input is floating, not a dead gate.
- If the chip runs warm, suspect a floating input or an output shorted to another gate — CMOS should draw microamps at rest.