Pinout diagram
Used in Retro Machine Hubs
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Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | DRD6 | Data Bus | Input | TTL | Chip RAM Data bus bit 6. |
| 2 | DRD5 | Data Bus | Input | TTL | Chip RAM Data bus bit 5. |
| 3 | DRD4 | Data Bus | Input | TTL | Chip RAM Data bus bit 4. |
| 4 | DRD3 | Data Bus | Input | TTL | Chip RAM Data bus bit 3. |
| 5 | DRD2 | Data Bus | Input | TTL | Chip RAM Data bus bit 2. |
| 6 | DRD1 | Data Bus | Input | TTL | Chip RAM Data bus bit 1. |
| 7 | DRD0 | Data Bus | Input | TTL | Chip RAM Data bus bit 0 (LSB). |
| 8 | M0V | I/O | Input | TTL | Mouse Port 1 Vertical quadrature pulse input (via 74LS157 U15 on A2000, or direct from DB9 Pin 1 on A500!). |
| 9 | M0H | I/O | Input | TTL | Mouse Port 1 Horizontal quadrature pulse input (DB9 Pin 2). If the mouse only moves in one axis, check Pins 8 and 9! |
| 10 | RGA8 | Address Bus | Input | TTL | Register Address Bus bit 8 from Agnus. |
| 11 | RGA7 | Address Bus | Input | TTL | Register Address Bus bit 7. |
| 12 | RGA6 | Address Bus | Input | TTL | Register Address Bus bit 6. |
| 13 | VSS1 | Ground | Power | 0 V | Primary digital ground. |
| 14 | RGA5 | Address Bus | Input | TTL | Register Address Bus bit 5. |
| 15 | RGA4 | Address Bus | Input | TTL | Register Address Bus bit 4. |
| 16 | RGA3 | Address Bus | Input | TTL | Register Address Bus bit 3. |
| 17 | RGA2 | Address Bus | Input | TTL | Register Address Bus bit 2. |
| 18 | RGA1 | Address Bus | Input | TTL | Register Address Bus bit 1 (LSB). |
| 19 | VCC (+5V) | Power | Power | +5 V | Main +5 V supply. |
| 20 | R0 | Analog | Output | TTL | Digital RED output bit 0 (LSB). |
| 21 | R1 | Analog | Output | TTL | Digital RED output bit 1. |
| 22 | R2 | Analog | Output | TTL | Digital RED output bit 2. |
| 23 | R3 | Analog | Output | TTL | Digital RED output bit 3 (MSB). |
| 24 | B0 | Analog | Output | TTL | Digital BLUE output bit 0 (LSB). |
| 25 | B1 | Analog | Output | TTL | Digital BLUE output bit 1. |
| 26 | B2 | Analog | Output | TTL | Digital BLUE output bit 2. |
| 27 | B3 | Analog | Output | TTL | Digital BLUE output bit 3 (MSB). |
| 28 | G0 | Analog | Output | TTL | Digital GREEN output bit 0 (LSB). |
| 29 | G1 | Analog | Output | TTL | Digital GREEN output bit 1. |
| 30 | G2 | Analog | Output | TTL | Digital GREEN output bit 2. |
| 31 | G3 | Analog | Output | TTL | Digital GREEN output bit 3 (MSB). |
| 32 | /BURST | Control | Output | TTL, active low | Colourburst gate output. |
| 33 | /ZD (ZDBP) | Control | Output | TTL | Zero Detect Background Pixel (for Genlock overlay transparency). |
| 34 | /CSYNC | Control | Input | TTL | Composite Sync input from Agnus. |
| 35 | 7MHZ | Clock / Timing | Input | TTL 7.09 MHz | 7.09 MHz pixel clock input. |
| 36 | CCK | Clock / Timing | Input | TTL 3.55 MHz | 3.55 MHz Colour Clock input from Agnus. |
| 37 | VSS2 | Ground | Power | 0 V | Secondary digital ground. |
| 38 | M1H | I/O | Input | TTL | Joystick/Mouse Port 2 Horizontal quadrature input (also reads Joystick 2 UP/LEFT in digital mode!). |
| 39 | M1V | I/O | Input | TTL | Joystick/Mouse Port 2 Vertical quadrature input (also reads Joystick 2 DOWN/RIGHT in digital mode!). |
| 40 | DRD15 | Data Bus | Input | TTL | Chip RAM Data bus bit 15 (MSB). |
| 41 | DRD14 | Data Bus | Input | TTL | Chip RAM Data bus bit 14. |
| 42 | DRD13 | Data Bus | Input | TTL | Chip RAM Data bus bit 13. |
| 43 | DRD12 | Data Bus | Input | TTL | Chip RAM Data bus bit 12. |
| 44 | DRD11 | Data Bus | Input | TTL | Chip RAM Data bus bit 11. |
| 45 | DRD10 | Data Bus | Input | TTL | Chip RAM Data bus bit 10. |
| 46 | DRD9 | Data Bus | Input | TTL | Chip RAM Data bus bit 9. |
| 47 | DRD8 | Data Bus | Input | TTL | Chip RAM Data bus bit 8. |
| 48 | DRD7 | Data Bus | Input | TTL | Chip RAM Data bus bit 7. |
Common uses and repair diagnostics
Named after 'Display Encoder', the 48-pin DIP MOS 8362 (OCS Denise) and its 100% pin-compatible drop-in upgrade MOS 8373 (ECS Super Denise, which adds Productivity 640x480 and SuperHiRes 1280x200 modes!) sit on the 16-bit Chip RAM data bus (DRD0-DRD15) and the 8-bit Register Address Bus (RGA1-RGA8) driven by Agnus. Denise serializes up to 6 bitplanes (32 colours, 64-colour Extra-Halfbrite, or 4096-colour Hold-And-Modify HAM6) plus 8 hardware sprites, looks up each pixel in thirty-two 12-bit colour palette registers ($DFF180-$DFF1BE), outputs 12-bit digital RGB (R0-R3, G0-G3, B0-B3) to the external video DAC/buffer, and decodes the X/Y optical quadrature rollers for Mouse/Joystick Ports 1 and 2 (M0H, M0V, M1H, M1V)!
Used in the Amiga 1000, Amiga 500, Amiga 500+ (8373 Super Denise), Amiga 2000, and Amiga 3000 (8373 Super Denise). Because Denise outputs all 12 digital RGB bits on Pins 20-31, the open-source RGBtoHDMI adapter board sits right between Denise and its 48-pin socket to capture pixel-perfect digital HDMI video.
- Wait before blaming CIA-A if the Amiga mouse cursor only moves left/right or up/down! CIA-A only reads the Left Mouse Button (/FIR0); the actual X/Y mouse movement rollers (M0H/M0V) feed straight into Denise Pins 8 and 9 (and Joystick 2 directions feed into Denise Pins 38 and 39)!
- Missing a colour tint or posterized gradients on RGB video: check the 12 digital colour bits R0-R3 (Pins 20-23), B0-B3 (Pins 24-27), and G0-G3 (Pins 28-31) entering the 40-pin hybrid video DAC.