Pinout diagram
Used in Retro Machine Hubs
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Summary specifications
Technology
HMOS
Operating Voltage
+5 V +/-5% (VCC pin 14, GND pins 15 and 38)
Clock
7.5 MHz in the Sinclair QL (rated 8 MHz or 10 MHz)
Address Bus
20-bit in DIP-48 (A0-A19 = 1 MB linear space)
Data Bus
8-bit bidirectional (D0-D7)
Bus Handshake
Asynchronous (/AS, /DS, R/W, /DTACK)
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | A0 | Address Bus | Tri-state output | TTL | Address bit 0 (byte select). Unlike the 16-bit 68000, the 8-bit 68008 has a real A0 pin. |
| 2 | A1 | Address Bus | Tri-state output | TTL | Address bus bit 1. |
| 3 | A2 | Address Bus | Tri-state output | TTL | Address bus bit 2. |
| 4 | A3 | Address Bus | Tri-state output | TTL | Address bus bit 3. |
| 5 | A4 | Address Bus | Tri-state output | TTL | Address bus bit 4. |
| 6 | A5 | Address Bus | Tri-state output | TTL | Address bus bit 5. |
| 7 | A6 | Address Bus | Tri-state output | TTL | Address bus bit 6. |
| 8 | A7 | Address Bus | Tri-state output | TTL | Address bus bit 7. |
| 9 | A8 | Address Bus | Tri-state output | TTL | Address bus bit 8. |
| 10 | A9 | Address Bus | Tri-state output | TTL | Address bus bit 9. |
| 11 | A10 | Address Bus | Tri-state output | TTL | Address bus bit 10. |
| 12 | A11 | Address Bus | Tri-state output | TTL | Address bus bit 11. |
| 13 | A12 | Address Bus | Tri-state output | TTL | Address bus bit 12. |
| 14 | VCC | Power | Power | +5 V | Main +5 V supply pin. |
| 15 | GND | Ground | Power | 0 V | Primary digital ground (also connect pin 38). |
| 16 | A13 | Address Bus | Tri-state output | TTL | Address bus bit 13. |
| 17 | A14 | Address Bus | Tri-state output | TTL | Address bus bit 14. |
| 18 | A15 | Address Bus | Tri-state output | TTL | Address bus bit 15. |
| 19 | A16 | Address Bus | Tri-state output | TTL | Address bus bit 16. |
| 20 | A17 | Address Bus | Tri-state output | TTL | Address bus bit 17. |
| 21 | A18 | Address Bus | Tri-state output | TTL | Address bus bit 18 (selects Sinclair QL RAM at $40000). |
| 22 | A19 | Address Bus | Tri-state output | TTL | Address bus bit 19 (MSB in DIP-48 package). |
| 23 | D7 | Data Bus | Bidirectional | TTL | Data bus bit 7 (MSB). |
| 24 | D6 | Data Bus | Bidirectional | TTL | Data bus bit 6. |
| 25 | D5 | Data Bus | Bidirectional | TTL | Data bus bit 5. |
| 26 | D4 | Data Bus | Bidirectional | TTL | Data bus bit 4. |
| 27 | D3 | Data Bus | Bidirectional | TTL | Data bus bit 3. |
| 28 | D2 | Data Bus | Bidirectional | TTL | Data bus bit 2. |
| 29 | D1 | Data Bus | Bidirectional | TTL | Data bus bit 1. |
| 30 | D0 | Data Bus | Bidirectional | TTL | Data bus bit 0 (LSB). |
| 31 | /DS | Control | Tri-state output | TTL, active low | Data Strobe. Asserts low when D0-D7 data is valid during a read or write cycle. |
| 32 | /AS | Control | Tri-state output | TTL, active low | Address Strobe. Asserts low when a valid address is on A0-A19. |
| 33 | R/W | Control | Tri-state output | TTL | Read/Write (High = Read, Low = Write). |
| 34 | /DTACK | Control | Input | TTL, active low | Data Transfer Acknowledge. On the Sinclair QL, ZX8301 ULA generates /DTACK. If stuck high, the CPU freezes on its first cycle. |
| 35 | /BG | Control | Output | TTL, active low | Bus Grant output for DMA. |
| 36 | /BR | Control | Input | TTL, active low | Bus Request input. |
| 37 | CLK | Clock / Timing | Input | TTL clock | System clock input (7.5 MHz from ZX8301 on the Sinclair QL). |
| 38 | GND | Ground | Power | 0 V | Secondary digital ground. |
| 39 | /HALT | Control | Bidirectional | Open-drain, active low | Bidirectional Halt. Driven low with /RESET at power-up; driven low by the CPU itself on a Double Bus Fault. |
| 40 | /RESET | Control | Bidirectional | Open-drain, active low | Bidirectional Reset. Driven low by external reset circuit, or pulsed low by the 68008 RESET instruction. |
| 41 | /BERR | Control | Input | TTL, active low | Bus Error input. |
| 42 | /IPL2/0 | Control | Input | TTL, active low | Combined Interrupt Priority Level 0 and 2 input (tied together inside the 48-pin package). |
| 43 | /IPL1 | Control | Input | TTL, active low | Interrupt Priority Level 1 input. |
| 44 | FC2 | Control | Output | TTL | Processor Function Code bit 2 (High = Supervisor Mode, Low = User Mode). |
| 45 | FC1 | Control | Output | TTL | Processor Function Code bit 1. |
| 46 | FC0 | Control | Output | TTL | Processor Function Code bit 0 (FC2:0 = 111 indicates Interrupt Acknowledge cycle). |
| 47 | E | Clock / Timing | Output | TTL clock | 6800-family Enable clock output (CLK divided by 10). |
| 48 | /VPA | Control | Input | TTL, active low | Valid Peripheral Address (autovector interrupt / synchronous 6800 peripheral cycle). |
Common uses and repair diagnostics
The Motorola MC68008 wraps the complete 32-bit programmer's model of the MC68000 (eight 32-bit data registers D0-D7 and eight 32-bit address registers A0-A7) inside a 48-pin DIP with an 8-bit external data bus (D0-D7) and a 20-bit address bus (A0-A19, 1 MB address range). Unlike the 64-pin 68000 (which has /UDS and /LDS byte strobes and no A0 pin), the 68008 brings out a true byte address pin A0 (pin 1) and a single /DS data strobe (pin 31). Notice also that the 48-pin DIP combines /IPL0 and /IPL2 onto a single pin (pin 42) so only four interrupt levels (0, 2, 5, 7) can be encoded externally.
The MC68008 is the CPU of the Sinclair QL (running at 7.5 MHz) and was also used in the Luxor ABC 1600 and industrial controllers. Because its data bus is 8 bits wide, fetching a 16-bit instruction takes two bus cycles and fetching the 32-bit reset SSP/PC vectors from ROM ($00000-$00007) takes eight byte reads.
- Check Pin 39 (/HALT) and Pin 40 (/RESET): both must go low on power-up and release high together. If /RESET goes high (~5 V) and /HALT immediately drops back to 0 V, the 68008 encountered a Double Bus Fault reading the boot ROM or low RAM.
- Scope Pin 34 (/DTACK): on the Sinclair QL, the ZX8301 Master ULA drives /DTACK low on every memory access. If /DTACK stays stuck high, the CPU freezes permanently on its first instruction fetch.
- Check Pin 14 (+5 V) and Pins 15 and 38 (GND), plus a clean 7.5 MHz clock on Pin 37 (CLK).