Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | Q12 | I/O | Output | CMOS push-pull | Counter stage 12 output (MSB, divide by 4096). Toggles on every 2048th falling clock edge. |
| 2 | Q6 | I/O | Output | CMOS push-pull | Counter stage 6 output (divide by 64). Toggles on every 32nd falling clock edge. |
| 3 | Q5 | I/O | Output | CMOS push-pull | Counter stage 5 output (divide by 32). Toggles on every 16th falling clock edge. |
| 4 | Q7 | I/O | Output | CMOS push-pull | Counter stage 7 output (divide by 128). Toggles on every 64th falling clock edge. |
| 5 | Q4 | I/O | Output | CMOS push-pull | Counter stage 4 output (divide by 16). Toggles on every 8th falling clock edge. |
| 6 | Q3 | I/O | Output | CMOS push-pull | Counter stage 3 output (divide by 8). Toggles on every 4th falling clock edge. |
| 7 | Q2 | I/O | Output | CMOS push-pull | Counter stage 2 output (divide by 4). Toggles on every 2nd falling clock edge. |
| 8 | VSS | Ground | Power | 0 V | Ground return. |
| 9 | Q1 | I/O | Output | CMOS push-pull | Counter stage 1 output (LSB, divide by 2). Toggles on every falling clock edge. |
| 10 | CLOCK | Clock / Timing | Input | CMOS, falling edge | Clock input, negative-edge triggered. The counter advances on the high-to-low transition. |
| 11 | RESET | Control | Input | CMOS, 0 V / VDD, active high | Master reset, active HIGH. Pulling this pin high clears all 12 stages to zero. Must be held low for normal counting. |
| 12 | Q9 | I/O | Output | CMOS push-pull | Counter stage 9 output (divide by 512). Toggles on every 256th falling clock edge. |
| 13 | Q8 | I/O | Output | CMOS push-pull | Counter stage 8 output (divide by 256). Toggles on every 128th falling clock edge. |
| 14 | Q10 | I/O | Output | CMOS push-pull | Counter stage 10 output (divide by 1024). Toggles on every 512th falling clock edge. |
| 15 | Q11 | I/O | Output | CMOS push-pull | Counter stage 11 output (divide by 2048). Toggles on every 1024th falling clock edge. |
| 16 | VDD | Power | Power | +3 V to +15 V | Positive supply. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The CD4040 is the 4000-series 12-stage ripple-carry binary counter. On every falling clock edge the 12-bit count advances by one; the active-high reset clears all stages to zero. The twelve Q outputs are scattered around the package in no obvious order — Q1 is on pin 9, Q2 on pin 7, Q3 on pin 6, and so on — so the pinout must be transcribed from the datasheet, not inferred. The part is the standard divide-by-N building block on boards that need a slow clock derived from a faster one, and the twelve stages give a maximum divide of 4096 from a single chip.
The CD4040 is the standard 12-stage ripple counter on boards that need to divide a clock by a large power of two. It derives a 1 Hz clock from a 4096 Hz source, generates slow timing strobes from a faster master clock, and builds the long-duration timers that some retro boards use for watchdogs and power-on delays. The twelve stages give a maximum divide of 4096 from a single chip, and the negative-edge clock lets it sit directly on the output of a positive-edge driven flip-flop without an inverter.
The trap with the CD4040 is the output pin order. Q1 is on pin 9, Q2 on pin 7, Q3 on pin 6, and the rest are scattered similarly. A board laid out assuming Q1 is on pin 1 will wire the wrong division ratio to the wrong stage, so always verify against the datasheet.
- Confirm pin 16 (VDD) is within 3 to 15 V and pin 8 (VSS) is at 0 V. Overvoltage or reversed rails kill CMOS instantly.
- Hold RESET low and clock CLOCK with a clean signal: Q1 should toggle on every falling edge, Q2 on every second falling edge, and so on. A stuck output means a dead counter stage.
- Pull RESET high and check all Q outputs go low. If RESET does not work, the pin is damaged or tied incorrectly.
- If the counter skips counts, scope the clock — a slow or bouncing edge can double-clock the counter. Remember the clock is negative-edge triggered.
- If the chip runs warm, suspect a floating input — CMOS should draw microamps at rest.