Pinout diagram
Summary specifications
Technology
HMOS (MC68000) / HCMOS (MC68HC000)
Operating Voltage
+5 V, plus or minus 5%
Clock Speed
4 MHz to 12.5 MHz (HC up to 16 MHz)
Address Bus
24-bit, 16 MB linear addressing (A1 to A23)
Data Bus
16-bit, bidirectional (D0 to D15)
Internal Registers
32-bit, eight data and eight address registers
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 4. |
| 2 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 3. |
| 3 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 2. |
| 4 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 1. |
| 5 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 0. |
| 6 | /AS | Control | Output | TTL, active low | Active low. Address strobe. Low when a valid address is on the bus. |
| 7 | /UDS | Control | Output | TTL, active low | Active low. Upper data strobe. Low for the high byte (D8 to D15). |
| 8 | /LDS | Control | Output | TTL, active low | Active low. Lower data strobe. Low for the low byte (D0 to D7). |
| 9 | R/W | Control | Output | TTL | Read / Write. High reads, low writes. |
| 10 | /DTACK | Control | Input | TTL, active low | Active low. Data transfer acknowledge. Driven low by the addressed device to end a bus cycle. |
| 11 | /BG | Control | Output | TTL, active low | Active low. Bus grant. Asserted to pass bus mastership to a requester. |
| 12 | /BGACK | Control | Bidirectional | TTL, active low | Active low. Bus grant acknowledge. Driven low by the new master to confirm it owns the bus. |
| 13 | /BR | Control | Input | TTL, active low | Active low. Bus request. Held low by a device that wants the bus. |
| 14 | VCC | Power | Power | +5 V | Positive supply (one of two VCC pins). |
| 15 | CLK | Clock / Timing | Input | TTL clock | Single-phase clock input. All timing derives from this pin. |
| 16 | GND | Ground | Power | 0 V | Ground (one of two GND pins). |
| 17 | /HALT | Control | Bidirectional | TTL, active low | Active low. Halt. Pulled low to stop the CPU; the CPU drives it low on a double bus fault. |
| 18 | /RESET | Control | Bidirectional | TTL, active low | Active low. Reset. Bidirectional open-drain; low resets the CPU, and the CPU drives it low on a fault. |
| 19 | /VMA | Control | Output | TTL, active low | Active low. Valid memory address. Signalled to 6800-family peripherals that the address is valid. |
| 20 | E | Clock / Timing | Output | TTL clock | Enable clock. A 6800-bus compatibility clock at one tenth of the CPU clock. |
| 21 | /VPA | Control | Input | TTL, active low | Active low. Valid peripheral address. Asserted to force a 6800-family synchronous bus cycle. |
| 22 | /BERR | Control | Input | TTL, active low | Active low. Bus error. Low to abort the current cycle and raise an exception. |
| 23 | /IPL2 | Control | Input | TTL, active low | Active low. Interrupt priority level bit 2 (most significant). |
| 24 | /IPL1 | Control | Input | TTL, active low | Active low. Interrupt priority level bit 1. |
| 25 | /IPL0 | Control | Input | TTL, active low | Active low. Interrupt priority level bit 0 (least significant). Level 7 is non-maskable. |
| 26 | FC2 | Control | Output | TTL | Function code bit 2. With FC1 and FC0 indicates the cycle type (user/supervisor, program/data). |
| 27 | FC1 | Control | Output | TTL | Function code bit 1. |
| 28 | FC0 | Control | Output | TTL | Function code bit 0. All three high marks an interrupt acknowledge. |
| 29 | A1 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 1. The 68000 has no A0; byte selection is by UDS and LDS. |
| 30 | A2 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 2. |
| 31 | A3 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 3. |
| 32 | A4 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 4. |
| 33 | A5 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 5. |
| 34 | A6 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 6. |
| 35 | A7 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 7. |
| 36 | A8 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 8. |
| 37 | A9 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 9. |
| 38 | A10 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 10. |
| 39 | A11 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 11. |
| 40 | A12 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 12. |
| 41 | A13 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 13. |
| 42 | A14 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 14. |
| 43 | A15 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 15. |
| 44 | A16 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 16. |
| 45 | A17 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 17. |
| 46 | A18 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 18. |
| 47 | A19 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 19. |
| 48 | A20 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 20. |
| 49 | VCC | Power | Power | +5 V | Positive supply (second of two VCC pins). |
| 50 | A21 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 21. |
| 51 | A22 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 22. |
| 52 | A23 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 23, the most significant address line (16 MB). |
| 53 | GND | Ground | Power | 0 V | Ground (second of two GND pins). |
| 54 | D15 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 15, the most significant data line. |
| 55 | D14 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 14. |
| 56 | D13 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 13. |
| 57 | D12 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 12. |
| 58 | D11 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 11. |
| 59 | D10 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 10. |
| 60 | D9 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 9. |
| 61 | D8 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 8. |
| 62 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 7. |
| 63 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 6. |
| 64 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 5. |
Common uses and repair diagnostics
The Motorola 68000 is the 16/32-bit CPU at the heart of the Amiga, the Atari ST, the original Macintosh and the Sega Mega Drive. It exposes a 24-bit address bus, a 16-bit data bus and an asynchronous bus handshake that lets it talk to slow peripherals without wait-state generators, and the MC68HC000 is the pin-compatible CMOS refresh of the original HMOS part.
The 68000 drives the Amiga, the Atari ST, the original Macintosh and the Sega Mega Drive. Its 24-bit address bus reaches 16 MB of linear memory, its 16-bit data bus moves a word at a time, and its asynchronous handshake — AS, UDS, LDS and DTACK — lets it talk to slow ROM or I/O without external wait-state logic. The function-code pins FC0 to FC2 separate user and supervisor space, and the three IPL pins encode a seven-level interrupt priority.
On the repair bench a 68000 board that will not boot is usually a clock, reset or DTACK problem rather than a dead CPU. Probe CLK (pin 15), then RESET (pin 18) and HALT (pin 17); both must be high after power-on. If DTACK (pin 10) never asserts, the CPU sits waiting forever — a classic sign of a bad ROM or a stuck address decode. The CMOS MC68HC000 is a pin-compatible, cooler-running replacement for the original HMOS part.
- Scope pin 15 (CLK) for a clean clock at the rated speed; no clock means the oscillator has failed, not the CPU.
- After reset, check pin 18 (RESET) and pin 17 (HALT) are both high. A line held low keeps the CPU halted.
- Probe AS (pin 6) during reset; it should pulse as the CPU fetches the vector. A flat AS with a good clock points to a stuck bus or a dead CPU.
- Check DTACK (pin 10). If it never goes low, the CPU waits forever; suspect the ROM or the address-decode logic, not the 68000.
- Verify both VCC pins (14 and 49) read 5 V and both GND pins (16 and 53) read 0 V; a missing bond on one supply pin causes erratic faults.