Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | PHI0 | Clock / Timing | Input | TTL clock | Phase 0 clock input. 1 MHz in C64 mode, 2 MHz in 80-column mode. |
| 2 | RDY | Control | Input | TTL | Ready. Pulled low to stretch the current read cycle. |
| 3 | /IRQ | Control | Input | TTL, active low | Active low. Maskable interrupt request. |
| 4 | /NMI | Control | Input | TTL, active low | Active low. Non-maskable interrupt. Always serviced; the CPU fetches the NMI vector. |
| 5 | AEC | Control | Input | TTL | Address Enable Control. Low floats the address bus and R/W so the VIC-IIe can drive them. |
| 6 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. |
| 7 | A0 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 0. Tri-stated when AEC is low. |
| 8 | A1 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 1. |
| 9 | A2 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 2. |
| 10 | A3 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 3. |
| 11 | A4 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 4. |
| 12 | A5 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 5. |
| 13 | A6 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 6. |
| 14 | A7 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 7. |
| 15 | A8 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 8. |
| 16 | A9 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 9. |
| 17 | A10 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 10. |
| 18 | A11 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 11. |
| 19 | A12 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 12. |
| 20 | A13 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 13. |
| 21 | GND | Ground | Power | 0 V | Ground. Single ground pin, as on the 6510. |
| 22 | A14 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 14. |
| 23 | A15 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 15, the most significant address line. |
| 24 | P6 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 6. The C128 Caps Lock / 40-80 key sense. This is the ONLY pin that differs from the 6510: P6 here versus P5 on the 6510, with the rest of the port shifted. |
| 25 | P5 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 5. In the C64: cassette motor control. |
| 26 | P4 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 4. In the C64: cassette switch sense. |
| 27 | P3 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 3. In the C64: cassette data out. |
| 28 | P2 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 2. In the C64: /CHAREN. |
| 29 | P1 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 1. In the C64: /HIRAM. |
| 30 | P0 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 0. In the C64: /LORAM. |
| 31 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 7. The data bus DESCENDS: D7 here at pin 31 down to D0 at pin 38. |
| 32 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 6. |
| 33 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 5. |
| 34 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 4. |
| 35 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 3. |
| 36 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 2. |
| 37 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 1. |
| 38 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 0. |
| 39 | R/W | Control | Output | TTL, 0 V / 5 V | Read / Write. High during a read, low during a write. Tri-stated when AEC is low. |
| 40 | /RES | Control | Input | TTL, active low | Active low. Reset. Held low on power-up to force the CPU to fetch the reset vector. |
Common uses and repair diagnostics
The MOS 8502 is the CPU of the Commodore 128: a 6510 derivative with a 7-bit I/O port (P0 to P6) that runs at 1 MHz in C64 mode and 2 MHz in 80-column mode. Pins 1 to 23 and 31 to 40 are identical to the 6510; the only pinout difference is pin 24, which is P6 on the 8502 versus P5 on the 6510, with the rest of the port shifted accordingly. Port bits 0 to 5 carry the same C64 functions as the 6510, which is what makes C64 mode work; bit 6 is the C128 Caps Lock / 40-80 key sense.
The 8502 is the Commodore 128 CPU. It runs at 1 MHz in C64 mode and 2 MHz in 80-column mode, where the VIC-IIe is not stealing cycles. Its 7-bit I/O port has one more bit than the 6510: bits 0 to 5 carry the same C64 functions (/LORAM, /HIRAM, /CHAREN, cassette data, cassette sense, cassette motor), which is what makes C64 mode work, and bit 6 is the C128 Caps Lock / 40-80 key sense. The port sequence is contiguous (P6 at 24 down to P0 at 30, no gap), unlike the 8501 which skips P5.
Pins 1 to 23 and 31 to 40 are identical to the 6510. The only pinout difference is pin 24: P6 on the 8502 versus P5 on the 6510, with the rest of the port shifted accordingly. This makes the 8502 very nearly a drop-in for the 6510, but the port bit assignments differ and the two are not interchangeable.
- Scope pin 1 (PHI0) for a clean clock. In C64 mode it should be 1 MHz; in 80-column mode 2 MHz.
- Check pin 6 (VCC) at 5 V and pin 21 (GND) at 0 V.
- Probe pin 5 (AEC); if it is stuck low the CPU never drives the bus.
- Read the I/O port register at $00/$01: a port bit that will not follow its data direction register points at a failed 8502.
- If the C128 boots in C64 mode but not C128 mode, check port bit 6 (P6, pin 24) — the 40-80 / Caps Lock sense.