Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | VSS | Ground | Power | 0 V | Ground. Both power pins are on the left-hand side: VSS here on pin 1, VCC on pin 12. On a 24-pin part that is genuinely surprising. |
| 2 | RX DATA | I/O | Input | TTL | Serial receive data input. The UART receive data line. |
| 3 | RX CLK | Clock / Timing | Input | TTL clock | Receive clock. Separate from TX CLK (pin 4), so you can run split baud rates. Usually tied together to one baud-rate clock. The control register divides by 1, 16 or 64. |
| 4 | TX CLK | Clock / Timing | Input | TTL clock | Transmit clock. Separate from RX CLK (pin 3). Usually tied together. The ÷1 setting only works if the clock is synchronous with the data, which catches people out. |
| 5 | /RTS | Control | Output | TTL, active low | Active low. Request to Send. The only handshake OUTPUT. There is no /DTR and no /DSR, so full RS-232 handshaking needs extra port bits elsewhere. |
| 6 | TX DATA | I/O | Output | TTL | Serial transmit data output. The UART transmit data line. |
| 7 | /IRQ | Control | Open-drain / open-collector | TTL, active low, open drain | Active low. Interrupt request, open-drain. Asserted on receive-data-ready, transmit-buffer-empty or a change in /DCD (pin 23). |
| 8 | CS0 | Control | Input | TTL, active high | Chip select 0. ACTIVE HIGH. All three selects must be satisfied: CS0 high, CS1 (pin 10) high, /CS2 (pin 9) low. |
| 9 | /CS2 | Control | Input | TTL, active low | Active low. Chip select 2. All three selects must be satisfied: CS0 (pin 8) high, CS1 (pin 10) high, /CS2 low. |
| 10 | CS1 | Control | Input | TTL, active high | Chip select 1. ACTIVE HIGH. All three selects must be satisfied: CS0 (pin 8) high, CS1 high, /CS2 (pin 9) low. Note the mixed polarity of the three selects. |
| 11 | RS | Address Bus | Input | TTL | Register Select. One select, giving two addressable registers per direction: control/status and transmit/receive data. The status register is where you read framing, parity and overrun errors. |
| 12 | VCC | Power | Power | +5 V | Positive supply. Both power pins are on the left-hand side: VSS on pin 1, VCC here on pin 12. Decouple with 100 nF close to the pin. |
| 13 | R/W | Control | Input | TTL | Read / Write. High reads a register, low writes one. The internal slash is NOT an active-low marker. |
| 14 | E | Clock / Timing | Input | TTL clock | Enable clock. The 6800 bus enable clock for register access. |
| 15 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 7. |
| 16 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 6. |
| 17 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 5. |
| 18 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 4. |
| 19 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 3. |
| 20 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 2. |
| 21 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 1. |
| 22 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 0. |
| 23 | /DCD | Control | Input | TTL, active low | Active low. Data Carrier Detect. Hardware handshake input. Going high also sets an interrupt flag, so an unconnected /DCD left floating produces phantom interrupts — tie it low if unused. |
| 24 | /CTS | Control | Input | TTL, active low | Active low. Clear to Send. Hardware handshake input. Low indicates the modem or remote device is ready to receive data. |
Common uses and repair diagnostics
The Motorola MC6850 ACIA (Asynchronous Communications Interface Adapter) is the serial UART for the 6800 family. The headline trap is the power: both supply pins are on the LEFT-HAND SIDE — VSS pin 1 and VCC pin 12, the two ends of the same row rather than opposite corners. On a 24-pin part that is genuinely surprising. TTL levels only — real RS-232 needs a level shifter (a MAX232 on a modern build, or a 1488/1489 pair period-correct).
The MC6850 ACIA is the serial UART for the 6800 family. Used in the BBC Micro serial port, the Dragon 32/64, the Tandy CoCo, countless 6800 and 6809 boards, and the Commodore PET's IEEE option. The headline trap is the power: both supply pins are on the LEFT-HAND SIDE — VSS pin 1 and VCC pin 12, the two ends of the same row rather than opposite corners. On a 24-pin part that is genuinely surprising.
Separate transmit and receive clocks, RX CLK (pin 3) and TX CLK (pin 4), so you can run split baud rates. They are usually tied together to one baud-rate clock. The control register divides by 1, 16 or 64 — and the ÷1 setting only works if the clock is synchronous with the data, which catches people out. Three chip selects with mixed polarity again: CS0 (pin 8) and CS1 (pin 10) active HIGH, /CS2 (pin 9) active LOW. One register select, RS (pin 11), giving two addressable registers per direction: control/status and transmit/receive data. The status register is where you read framing, parity and overrun errors.
/DCD (pin 23) and /CTS (pin 24) are hardware handshake INPUTS; /RTS (pin 5) is the only handshake OUTPUT. There is no /DTR and no /DSR, so full RS-232 handshaking needs extra port bits elsewhere. /DCD going high also sets an interrupt flag, so an unconnected /DCD left floating produces phantom interrupts — tie it low if unused. TTL levels only — real RS-232 needs a level shifter (a MAX232 on a modern build, or a 1488/1489 pair period-correct).
- Loop TX DATA (pin 6) back to RX DATA (pin 2) and confirm a character written reads back. That isolates the ACIA from the rest of the system.
- No clock on pins 3 (RX CLK) and 4 (TX CLK) means no serial activity at all — the first thing to check.
- A permanently set overrun or framing error with a good clock usually means the divider setting and the baud clock do not match.
- An unconnected /DCD (pin 23) left floating produces phantom interrupts. Tie it low if unused.
- Both power pins are on the left-hand side: VSS on pin 1, VCC on pin 12. Do not look for VCC on pin 24.