74LS138 Pinout — 3-to-8 Line Decoder

DIP-16 · 74-Series Logic · SN74LS138N / DM74LS138

Pinout diagram

Summary specifications

Technology Low-power Schottky TTL
Operating Voltage 4.75 V to 5.25 V (5 V nominal)
Propagation Delay 21 ns typical (address to output)
Enable Delay 19 ns typical (enable to output)
Supply Current 10 mA typical (ICC)
Logic Levels VIL max 0.8 V, VIH min 2.0 V, VOL max 0.5 V, VOH min 2.7 V

Full pin reference

Pin Name Group Direction Levels Description
1 A0 Address Bus Input TTL, 0 V / 5 V Address input, bit 0 (LSB). Selects which of Y0-Y7 is active.
2 A1 Address Bus Input TTL, 0 V / 5 V Address input, bit 1.
3 A2 Address Bus Input TTL, 0 V / 5 V Address input, bit 2 (MSB).
4 /E1 Control Input TTL, 0 V / 5 V, active low Enable input, active low. The decoder is enabled only when /E1, /E2 are both low and E3 is high; otherwise all outputs are high. TI marks this pin G2A on some datasheets; NXP and others mark it E1.
5 /E2 Control Input TTL, 0 V / 5 V, active low Enable input, active low. Same gating as /E1. TI marks this pin G2B on some datasheets; NXP and others mark it E2.
6 E3 Control Input TTL, 0 V / 5 V, active high Enable input, active high. The decoder is enabled only when E3 is high and /E1, /E2 are both low. TI marks this pin G1 on some datasheets; NXP and others mark it E3.
7 /Y7 Control Output TTL totem-pole, active low Active low. Decoded output 7. Low only when enabled and A2 A1 A0 = 111; high otherwise.
8 GND Ground Power 0 V Ground return.
9 /Y6 Control Output TTL totem-pole, active low Active low. Decoded output 6. Low only when enabled and A2 A1 A0 = 110.
10 /Y5 Control Output TTL totem-pole, active low Active low. Decoded output 5. Low only when enabled and A2 A1 A0 = 101.
11 /Y4 Control Output TTL totem-pole, active low Active low. Decoded output 4. Low only when enabled and A2 A1 A0 = 100.
12 /Y3 Control Output TTL totem-pole, active low Active low. Decoded output 3. Low only when enabled and A2 A1 A0 = 011.
13 /Y2 Control Output TTL totem-pole, active low Active low. Decoded output 2. Low only when enabled and A2 A1 A0 = 010.
14 /Y1 Control Output TTL totem-pole, active low Active low. Decoded output 1. Low only when enabled and A2 A1 A0 = 001.
15 /Y0 Control Output TTL totem-pole, active low Active low. Decoded output 0. Low only when enabled and A2 A1 A0 = 000.
16 VCC Power Power +5 V Positive supply. Decouple with 100 nF close to the pin.

Common uses and repair diagnostics

The 74LS138 is the 3-to-8 line decoder that turns up on almost every memory board of the era. Three address lines select one of eight active-low outputs; three enable inputs (two active low, one active high) gate the whole device, so several 74LS138s can be paralleled to decode a larger address space without extra glue. It is the part you reach for when a board needs to chip-select one of eight ROM, RAM or I/O blocks from a three-bit address field, and the active-low outputs mate directly with the active-low chip-selects of most memory and peripheral chips.

The 74LS138 is the memory decoder of choice on 8-bit and 16-bit boards. Three address lines select one of eight chip-selects, and the three enable inputs let several 74LS138s be ganged to decode a larger address field without any extra gates — a 5-to-32 decoder takes four 74LS138s and one inverter. The active-low outputs mate directly with the active-low chip-selects of most ROM, RAM and peripheral chips, which is why the part is so common on memory maps. It also works as a demultiplexer: feed the data into one of the active-low enables and use the address lines to route it to one of the eight outputs. The 74HC138 and 74HCT138 are the CMOS equivalents and share the same pinout.

  • With power off, probe pin 16 (VCC) to pin 8 (GND) for a low-ohms supply rail; a dead short or open points to a decoupling capacitor or the chip itself.
  • Power up and check pin 16 sits at 4.75 to 5.25 V. A sagging rail can make the decoder assert the wrong output, which on a memory board looks like a bad chip.
  • Confirm the enable inputs are in the active state: E1 and E2 low, E3 high. If all eight outputs sit high, the enables are usually the reason, not the address lines.
  • Drive A0-A2 through each of the eight combinations and check that exactly one output goes low each time. Two outputs low means a shorted output; none means a dead decoder.
  • If the board intermittently selects the wrong device, scope the enable inputs — a slow edge on E3 can let the decoder respond to a stale address for a few nanoseconds.

Datasheets and references

Related chips

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