Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | DIR | Control | Input | TTL, 0 V / 5 V | Direction control. When OE is low: DIR low drives B from A; DIR high drives A from B. When OE is high, DIR is ignored and both ports are high impedance. |
| 2 | A1 | I/O | Bidirectional | TTL 3-state | Port A, bit 1. Input or output depending on DIR; high impedance when OE is high. |
| 3 | A2 | I/O | Bidirectional | TTL 3-state | Port A, bit 2. |
| 4 | A3 | I/O | Bidirectional | TTL 3-state | Port A, bit 3. |
| 5 | A4 | I/O | Bidirectional | TTL 3-state | Port A, bit 4. |
| 6 | A5 | I/O | Bidirectional | TTL 3-state | Port A, bit 5. |
| 7 | A6 | I/O | Bidirectional | TTL 3-state | Port A, bit 6. |
| 8 | A7 | I/O | Bidirectional | TTL 3-state | Port A, bit 7. |
| 9 | A8 | I/O | Bidirectional | TTL 3-state | Port A, bit 8. |
| 10 | GND | Ground | Power | 0 V | Ground return for both ports. |
| 11 | B8 | I/O | Bidirectional | TTL 3-state | Port B, bit 8. Input or output depending on DIR; high impedance when OE is high. |
| 12 | B7 | I/O | Bidirectional | TTL 3-state | Port B, bit 7. |
| 13 | B6 | I/O | Bidirectional | TTL 3-state | Port B, bit 6. |
| 14 | B5 | I/O | Bidirectional | TTL 3-state | Port B, bit 5. |
| 15 | B4 | I/O | Bidirectional | TTL 3-state | Port B, bit 4. |
| 16 | B3 | I/O | Bidirectional | TTL 3-state | Port B, bit 3. |
| 17 | B2 | I/O | Bidirectional | TTL 3-state | Port B, bit 2. |
| 18 | B1 | I/O | Bidirectional | TTL 3-state | Port B, bit 1. |
| 19 | /OE | Control | Input | TTL, 0 V / 5 V, active low | Output enable, active low. When low, the transceiver drives in the direction set by DIR; when high, both ports are high impedance. |
| 20 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The 74LS245 is the octal bidirectional 3-state bus transceiver — eight pairs of A and B pins, one direction pin and one active-low output enable. When the enable is low, the direction pin decides whether data flows from A to B or from B to A; when the enable is high, both ports go to high impedance. It is the part you reach for whenever two boards or two sections of a board need to share a bidirectional data bus, and unlike the unidirectional 74LS244 it has the clean A-on-one-side, B-on-the-other pinout that makes layout simple.
The 74LS245 is the bidirectional bus transceiver on boards that need to share a data bus between two drivers. It sits between the CPU and the memory, between the main board and an expansion card, or between two sections of a board that take turns driving the same lines. The direction pin lets the CPU read from or write to the bus without re-wiring, and the active-low enable lets the transceiver sit on a shared bus without contention. The 74HC245 and 74HCT245 are the CMOS equivalents and share the same pinout. Note that the 74LS245 is not a drop-in for the 74LS244 — the 244 is unidirectional with two nibble enables, the 245 is bidirectional with one direction pin, and the pin assignments are different.
- With power off, probe pin 20 (VCC) to pin 10 (GND) for a low-ohms supply rail; a dead short or open points to a decoupling capacitor or the chip itself.
- Power up and check pin 20 sits at 4.75 to 5.25 V. A sagging rail can make a 3-state port float when it should drive, which on a bus looks like a stuck line.
- Drive a port A pin, set DIR low and OE low, and check the matching port B pin follows. Set DIR high and check the direction reverses. Set OE high and check both ports go high impedance.
- If a bus line is stuck high or low, lift OE and check whether the stuck level follows the chip or stays on the bus — a stuck bus points to another driver, a stuck chip points here.
- Scope OE and DIR during bus cycles; a slow edge on either can let two transceivers fight for a few nanoseconds, which is enough to glitch the bus and corrupt a read or write.