Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | /1CLR | Control | Input | TTL, 0 V / 5 V, active low | Flip-flop 1 clear. Asynchronous, active low: pulling this pin low forces 1Q low and /1Q high, regardless of the clock. Must be held high for normal clocked operation. |
| 2 | 1D | I/O | Input | TTL, 0 V / 5 V | Flip-flop 1 data input. The level here is transferred to Q1 on the rising edge of 1CLK. |
| 3 | 1CLK | Clock / Timing | Input | TTL, rising edge | Flip-flop 1 clock. Positive-edge triggered: Q1 takes the 1D level on the low-to-high transition. |
| 4 | /1PRE | Control | Input | TTL, 0 V / 5 V, active low | Flip-flop 1 preset. Asynchronous, active low: pulling this pin low forces 1Q high and /1Q low, regardless of the clock. Must be held high for normal clocked operation. |
| 5 | 1Q | I/O | Output | TTL totem-pole | Flip-flop 1 Q output. Takes the 1D level on the rising clock edge; cleared low by /1CLR; preset high by /1PRE. |
| 6 | /1Q | I/O | Output | TTL totem-pole | Flip-flop 1 inverted Q output (/Q). Always the complement of 1Q. This is the active low complement of the Q output. |
| 7 | GND | Ground | Power | 0 V | Ground return for both flip-flops. |
| 8 | /2Q | I/O | Output | TTL totem-pole | Flip-flop 2 inverted Q output (/Q). Always the complement of 2Q. This is the active low complement of the Q output. |
| 9 | 2Q | I/O | Output | TTL totem-pole | Flip-flop 2 Q output. Takes the 2D level on the rising clock edge; cleared low by /2CLR; preset high by /2PRE. |
| 10 | /2PRE | Control | Input | TTL, 0 V / 5 V, active low | Flip-flop 2 preset. Asynchronous, active low: pulling this pin low forces 2Q high and /2Q low, regardless of the clock. Must be held high for normal clocked operation. |
| 11 | 2CLK | Clock / Timing | Input | TTL, rising edge | Flip-flop 2 clock. Positive-edge triggered: 2Q takes the 2D level on the low-to-high transition. |
| 12 | 2D | I/O | Input | TTL, 0 V / 5 V | Flip-flop 2 data input. The level here is transferred to 2Q on the rising edge of 2CLK. |
| 13 | /2CLR | Control | Input | TTL, 0 V / 5 V, active low | Flip-flop 2 clear. Asynchronous, active low: pulling this pin low forces 2Q low and /2Q high, regardless of the clock. Must be held high for normal clocked operation. |
| 14 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The 74LS74 is the dual D-type positive-edge-triggered flip-flop — two independent flip-flops in a 14-pin DIP, each with its own data, clock, preset and clear. The clock is edge-triggered on the rising edge; the preset and clear are asynchronous and both active low, so pulling either pin low forces the Q output to the preset or cleared state immediately, regardless of the clock. It is the part you reach for whenever a signal needs to be latched on an edge, divided by two, or synchronised to a clock domain.
The 74LS74 is the standard edge-triggered flip-flop on boards that need to latch a signal on a clock edge or divide a clock by two. It synchronises asynchronous inputs to the system clock, builds the toggle flip-flops that halve a clock frequency, and holds address or control bits stable across a cycle where a transparent latch would let them through. The asynchronous preset and clear are the route to a power-on reset that forces a known state before the first clock edge, which is why the part turns up in reset and debounce circuits as often as in clocked logic. The 74HC74 and 74HCT74 are the CMOS equivalents and share the same pinout.
- With power off, probe pin 14 (VCC) to pin 7 (GND) for a low-ohms supply rail; a dead short or open points to a decoupling capacitor or the chip itself.
- Power up and check pin 14 sits at 4.75 to 5.25 V. A sagging rail can cause spurious clocking as the input thresholds shift.
- Hold 1CLR and 1PRE high (or confirm the board ties them high) and clock 1CLK: 1Q must take the 1D level on the rising edge. A Q that does not change suggests a dead flip-flop or a floating D input.
- Pull 1CLR low and check 1Q goes low; pull 1PRE low and check 1Q goes high. If neither works the asynchronous inputs are damaged, which is a common failure mode on this part.
- Check the clock edge is clean and monotonic at the 1CLK and 2CLK pins; a slow or bouncing edge can double-clock the flip-flop and make Q appear to skip or toggle twice.