Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | X1 | Clock / Timing | Input | Crystal | Crystal input 1. Connect one side of the crystal here; the other goes to X2 (pin 2). The on-chip oscillator divides by two. |
| 2 | X2 | Clock / Timing | Output | Crystal | Crystal input 2. Drives the other side of the crystal. |
| 3 | RESET OUT | Control | Output | TTL, active high | Reset output. ACTIVE HIGH. Driven high while the CPU is resetting, to reset the rest of the board. Distinct from /RESET (pin 36), the reset input — two different reset pins at opposite ends of the package, an easy mix-up. |
| 4 | SOD | I/O | Output | TTL | Serial Output Data. Set by the SIM instruction — bit-banged serial output with no UART. |
| 5 | SID | I/O | Input | TTL | Serial Input Data. Read by the RIM instruction — bit-banged serial input with no UART. |
| 6 | TRAP | Control | Input | TTL, active high | Trap. Non-maskable, highest-priority interrupt. Both edge- and level-triggered. Cannot be disabled by software. |
| 7 | RST 7.5 | Control | Input | TTL, active high | Restart 7.5. Edge-triggered. Second-highest priority. Maskable via the SIM instruction. |
| 8 | RST 6.5 | Control | Input | TTL, active high | Restart 6.5. Level-triggered. Third-highest priority. Maskable via the SIM instruction. |
| 9 | RST 5.5 | Control | Input | TTL, active high | Restart 5.5. Level-triggered. Fourth-highest priority. Maskable via the SIM instruction. |
| 10 | INTR | Control | Input | TTL, active high | Interrupt Request. Lowest priority. Level-triggered. The CPU acknowledges with /INTA (pin 11). |
| 11 | /INTA | Control | Output | TTL, active low | Active low. Interrupt Acknowledge. Low in response to INTR (pin 10), indicating the CPU is accepting the interrupt. |
| 12 | AD0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Address/Data bit 0. MULTIPLEXED: carries A0 during the first clock of each machine cycle and D0 afterwards. ALE (pin 30) high marks the address phase. An external 74LS373 latch uses ALE to recover the low address byte. |
| 13 | AD1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Address/Data bit 1. Multiplexed: A1 then D1. |
| 14 | AD2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Address/Data bit 2. Multiplexed: A2 then D2. |
| 15 | AD3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Address/Data bit 3. Multiplexed: A3 then D3. |
| 16 | AD4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Address/Data bit 4. Multiplexed: A4 then D4. |
| 17 | AD5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Address/Data bit 5. Multiplexed: A5 then D5. |
| 18 | AD6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Address/Data bit 6. Multiplexed: A6 then D6. |
| 19 | AD7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Address/Data bit 7. Multiplexed: A7 then D7. |
| 20 | VSS | Ground | Power | 0 V | Ground. |
| 21 | A8 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 8. A8-A15 (pins 21-28) are address-only — NOT multiplexed, unlike AD0-AD7. |
| 22 | A9 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 9. |
| 23 | A10 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 10. |
| 24 | A11 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 11. |
| 25 | A12 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 12. |
| 26 | A13 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 13. |
| 27 | A14 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 14. |
| 28 | A15 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 15, the most significant address line. |
| 29 | S0 | Control | Output | TTL | Status bit 0. Together with S1 (pin 33) and IO/M (pin 34) encodes the machine cycle type: opcode fetch, memory read, memory write, I/O read, I/O write. |
| 30 | ALE | Control | Output | TTL | Address Latch Enable. High during the first clock of each machine cycle to strobe the low address byte into an external 74LS373 latch. No ALE means no machine cycles are completing. |
| 31 | /WR | Control | Output | TTL, active low | Active low. Write strobe. Low when the CPU is writing data to memory or an I/O port. |
| 32 | /RD | Control | Output | TTL, active low | Active low. Read strobe. Low when the CPU is reading data from memory or an I/O port. |
| 33 | S1 | Control | Output | TTL | Status bit 1. Together with S0 (pin 29) and IO/M (pin 34) encodes the machine cycle type. |
| 34 | IO/M | Control | Output | TTL | IO/Memory select. HIGH selects an I/O port, LOW selects memory. The internal slash is NOT an active-low indicator — describe the two levels, do not treat it as a leading-slash active-low name. |
| 35 | READY | Control | Input | TTL, active high | Ready. ACTIVE HIGH. Low stretches the machine cycle for slow memory or I/O. A READY held low stalls the CPU silently. |
| 36 | /RESET | Control | Input | TTL, active low | Active low. Reset INPUT. Held low for at least three clock cycles to reset the CPU. Distinct from RESET OUT (pin 3), the active-high reset output for the rest of the board. |
| 37 | CLK OUT | Clock / Timing | Output | TTL clock | Clock output. Half the crystal frequency. A 6.144 MHz crystal gives 3.072 MHz here. Proving the oscillator works. |
| 38 | HLDA | Control | Output | TTL | Hold Acknowledge. High in response to HOLD (pin 39), indicating the CPU has released the buses for DMA. |
| 39 | HOLD | Control | Input | TTL, active high | Hold request. ACTIVE HIGH. Low tri-states the buses for DMA; the CPU acknowledges with HLDA (pin 38). |
| 40 | VCC | Power | Power | +5 V | Positive supply. Single +5 V rail — a huge improvement over the 8080's three rails. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The Intel 8085A is the 8080 done properly: ONE +5 V rail (pin 40) instead of three, and an on-chip clock oscillator — crystal straight across X1/X2 (pins 1, 2), divided by two, with the result available on CLK OUT (pin 37). A 6.144 MHz crystal gives 3.072 MHz. The headline is the multiplexed address/data bus: AD0-AD7 (pins 12-19) carry A0-A7 during the first clock of each machine cycle and D0-D7 afterwards; ALE (pin 30) going high marks the address phase and is what an external 74LS373 latch uses to recover the low address byte. Anyone probing AD0-AD7 expecting a plain data bus will see nonsense, so say this plainly.
The 8085A is the 8080 done properly: ONE +5 V rail (pin 40) instead of three, and an on-chip clock oscillator — crystal straight across X1/X2 (pins 1, 2), divided by two, with the result available on CLK OUT (pin 37). A 6.144 MHz crystal gives 3.072 MHz.
The headline is the multiplexed address/data bus. AD0-AD7 (pins 12-19) carry A0-A7 during the first clock of each machine cycle and D0-D7 afterwards; ALE (pin 30) going high marks the address phase and is what an external 74LS373 latch uses to recover the low address byte. A8-A15 (pins 21-28) are address-only. Anyone probing AD0-AD7 expecting a plain data bus will see nonsense, so say this plainly. This multiplexing is exactly why a 74LS373 sits next to an 8085 on every board.
Pin 34 IO/M: HIGH selects an I/O port, LOW selects memory. Intel prints it with a bar over the M, but it is not a leading-slash active-low name — describe the two levels. Pin 36 /RESET is the reset INPUT; pin 3 RESET OUT is an active-high reset OUTPUT for the rest of the board. Two different reset pins at opposite ends of the package — an easy mix-up.
Five interrupts in fixed hardware priority: TRAP (pin 6) highest and non-maskable, then RST 7.5 (pin 7), RST 6.5 (pin 8), RST 5.5 (pin 9), then INTR (pin 10) lowest. RST 7.5 is edge-triggered; RST 6.5 and RST 5.5 are level-triggered. TRAP is both. SID (pin 5) and SOD (pin 4) are a single-bit serial input and output driven by the RIM and SIM instructions — bit-banged serial with no UART.
- Check the crystal on X1/X2 (pins 1, 2) and half of it on CLK OUT (pin 37) — that proves the oscillator is running.
- Watch ALE (pin 30). No ALE means no machine cycles are completing.
- A /RESET (pin 36) held low, or READY (pin 35) held low, will stall the CPU silently. Probe both before condemning the chip.
- Do not confuse /RESET (pin 36, the input) with RESET OUT (pin 3, the output). They are at opposite ends of the package.
- Probing AD0-AD7 (pins 12-19) expecting a plain data bus will show nonsense — these are multiplexed. Watch ALE to see the address phase.