Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | /1E | Control | Input | TTL, 0 V / 5 V, active low | Decoder 1 enable, active low. When low, decoder 1 is active and one of 1Y0-1Y3 goes low; when high, all four 1Y outputs are high. |
| 2 | 1A0 | Address Bus | Input | TTL, 0 V / 5 V | Decoder 1 address input, bit 0 (LSB). |
| 3 | 1A1 | Address Bus | Input | TTL, 0 V / 5 V | Decoder 1 address input, bit 1 (MSB). |
| 4 | /1Y0 | Control | Output | TTL totem-pole, active low | Active low. Decoder 1 output 0. Low only when 1E is low and 1A1 1A0 = 00. |
| 5 | /1Y1 | Control | Output | TTL totem-pole, active low | Active low. Decoder 1 output 1. Low only when 1E is low and 1A1 1A0 = 01. |
| 6 | /1Y2 | Control | Output | TTL totem-pole, active low | Active low. Decoder 1 output 2. Low only when 1E is low and 1A1 1A0 = 10. |
| 7 | /1Y3 | Control | Output | TTL totem-pole, active low | Active low. Decoder 1 output 3. Low only when 1E is low and 1A1 1A0 = 11. |
| 8 | GND | Ground | Power | 0 V | Ground return for both decoders. |
| 9 | /2Y3 | Control | Output | TTL totem-pole, active low | Active low. Decoder 2 output 3. Low only when 2E is low and 2A1 2A0 = 11. |
| 10 | /2Y2 | Control | Output | TTL totem-pole, active low | Active low. Decoder 2 output 2. Low only when 2E is low and 2A1 2A0 = 10. |
| 11 | /2Y1 | Control | Output | TTL totem-pole, active low | Active low. Decoder 2 output 1. Low only when 2E is low and 2A1 2A0 = 01. |
| 12 | /2Y0 | Control | Output | TTL totem-pole, active low | Active low. Decoder 2 output 0. Low only when 2E is low and 2A1 2A0 = 00. |
| 13 | 2A1 | Address Bus | Input | TTL, 0 V / 5 V | Decoder 2 address input, bit 1 (MSB). |
| 14 | 2A0 | Address Bus | Input | TTL, 0 V / 5 V | Decoder 2 address input, bit 0 (LSB). |
| 15 | /2E | Control | Input | TTL, 0 V / 5 V, active low | Decoder 2 enable, active low. When low, decoder 2 is active and one of 2Y0-2Y3 goes low; when high, all four 2Y outputs are high. |
| 16 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The 74LS139 is the dual 2-to-4 line decoder — two independent decoders in one 16-pin package, each with two address inputs, one active-low enable and four active-low outputs. It is the smaller sibling of the 74LS138, and the two are not interchangeable: the 138 is one 3-to-8 decoder with three enables, the 139 is two 2-to-4 decoders with one enable each. The 139 turns up where a board needs two small decoders in one footprint — selecting one of four ROMs and one of four I/O blocks from two independent address fields.
The 74LS139 is the decoder you reach for when a board needs two small decoders in one package. Each half decodes a 2-bit address into one of four active-low outputs, and the two halves are fully independent, so one 74LS139 can select one of four ROMs and one of four I/O blocks from two unrelated address fields. It also works as a demultiplexer: feed data into the active-low enable and use the address lines to route it to one of the four outputs. The 74HC139 and 74HCT139 are the CMOS equivalents and share the same pinout. Note that the 74LS139 is not a drop-in for the 74LS138 — the 138 is one 3-to-8 decoder, the 139 is two 2-to-4 decoders, and the pin assignments are completely different.
- With power off, probe pin 16 (VCC) to pin 8 (GND) for a low-ohms supply rail; a dead short or open points to a decoupling capacitor or the chip itself.
- Power up and check pin 16 sits at 4.75 to 5.25 V. A sagging rail can make a decoder assert the wrong output, which on a memory board looks like a bad chip.
- Confirm each enable is in the active state when its decoder should be selecting. If all four outputs of one half sit high, the enable is usually the reason, not the address lines.
- Drive each half through all four address combinations and check that exactly one output goes low each time. Two outputs low means a shorted output; none means a dead decoder.
- If only one half misbehaves, the other is still usable — the two decoders are independent, so a single failed half does not always mean the whole chip is dead.