Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | 1Y | I/O | Output | TTL totem-pole | Gate 1 output. Low only when both 1A and 1B are high. Note: pin 1 is an OUTPUT on the 74LS02, unlike the 74LS00 where pin 1 is an input. |
| 2 | 1A | I/O | Input | TTL, 0 V / 5 V | Gate 1, input A. An unused input must be tied high, not left floating. |
| 3 | 1B | I/O | Input | TTL, 0 V / 5 V | Gate 1, input B. |
| 4 | 2Y | I/O | Output | TTL totem-pole | Gate 2 output. Low only when both 2A and 2B are high. |
| 5 | 2A | I/O | Input | TTL, 0 V / 5 V | Gate 2, input A. |
| 6 | 2B | I/O | Input | TTL, 0 V / 5 V | Gate 2, input B. |
| 7 | GND | Ground | Power | 0 V | Ground return for all four gates. |
| 8 | 3A | I/O | Input | TTL, 0 V / 5 V | Gate 3, input A. Note: pin 8 is an INPUT on the 74LS02, unlike the 74LS00 where pin 8 is an output. |
| 9 | 3B | I/O | Input | TTL, 0 V / 5 V | Gate 3, input B. |
| 10 | 3Y | I/O | Output | TTL totem-pole | Gate 3 output. Low only when both 3A and 3B are high. |
| 11 | 4A | I/O | Input | TTL, 0 V / 5 V | Gate 4, input A. Note: pin 11 is an INPUT on the 74LS02, unlike the 74LS00 where pin 11 is an output. |
| 12 | 4B | I/O | Input | TTL, 0 V / 5 V | Gate 4, input B. |
| 13 | 4Y | I/O | Output | TTL totem-pole | Gate 4 output. Low only when both 4A and 4B are high. |
| 14 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The 74LS02 holds four independent 2-input NOR gates in a 14-pin DIP, and it is the part that catches out anyone who assumes all 74-series quad gates share the 74LS00 pinout. The NOR gate puts its output on the first pin of each group: 1Y on pin 1, with the inputs on 2 and 3. Outputs land on 1, 4, 10 and 13 — the mirror of the 74LS00, whose outputs sit on 3, 6, 8 and 11. Dropping a 74LS02 into a board laid out for a 74LS00 (or vice versa) connects gate outputs to pins the board drives as inputs, and the fight that follows usually takes one side or the other with it.
The 74LS02 turns up wherever a board needs a NOR function — active-low decoders that combine several enable lines into one chip-select, reset logic that must go low when any of several fault conditions assert, and the classic cross-coupled NOR latch used as a debounce or power-on reset. Because the NOR is the natural complement of the NAND, a board that uses both will often pair a 74LS00 and a 74LS02 next to each other, and the two are not interchangeable despite the matching package.
The trap with the 74LS02 is the pinout. It looks like a 74LS00 from the top of the package — same 14-pin DIP, same supply pins — but the gate outputs are on pins 1, 4, 10 and 13, where the 74LS00 has its inputs. A 74LS02 dropped into a 74LS00 socket shorts gate outputs onto driven inputs, and the resulting contention usually kills one chip or the other within seconds. The 74HC02 and 74HCT02 are the CMOS equivalents; they share the 74LS02 pinout, not the 74LS00 pinout, so the same caution applies when moving between families.
- With power off, probe pin 14 (VCC) to pin 7 (GND) for a low-ohms supply rail; a dead short or open points to a decoupling capacitor or the chip itself.
- Power up and check pin 14 sits at 4.75 to 5.25 V. A sagging rail pulls the gate outputs out of spec and is often the real fault, not the gate.
- Drive both inputs of a gate high (or use the existing logic) and measure the output: it must pull below 0.5 V. A stuck-high output suggests a failed totem-pole transistor.
- Before substituting, confirm the board was laid out for a 74LS02 and not a 74LS00. The two share a package but put outputs on opposite pins, and swapping them shorts outputs to driven inputs.
- Tie one input of an unused gate to VCC through a 1 kR resistor and leave the other grounded; a floating LS input drifts high and makes the gate oscillate, coupling noise onto the rails.