Pinout diagram
Used in Retro Machine Hubs
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Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | OSC IN | Clock / Timing | Input | 14.318 MHz | Master 14.31818 MHz crystal oscillator input. |
| 2 | OSC OUT | Clock / Timing | Output | 14.318 MHz | Crystal oscillator output. |
| 3 | DA0 | Clock / Timing | Input | TTL | Display Address bit 0 input from MC6847 Pin 22 (synchronizes SAM's internal video counter). |
| 4 | /HS | Control | Input | TTL, active low | Horizontal Sync input from MC6847 Pin 38. |
| 5 | /FS | Control | Input | TTL, active low | Field Sync (Vertical Blank) input from MC6847 Pin 37 (resets SAM video address counter to top of screen). |
| 6 | R/W | Control | Input | TTL | CPU Read/Write input from 6809E. |
| 7 | /RESET | Control | Input | TTL, active low | System Reset input (clears all 16 SAM control bits at $FFC0-$FFDF to 0). |
| 8 | S2 | Control | Output | TTL | Device Select code bit 2 (feeds 74LS138 input C to generate PIA, ROM and Cart chip selects). |
| 9 | S1 | Control | Output | TTL | Device Select code bit 1 (feeds 74LS138 input B). |
| 10 | S0 | Control | Output | TTL | Device Select code bit 0 (feeds 74LS138 input A). |
| 11 | /WE | Control | Output | TTL, active low | DRAM Write Enable output. |
| 12 | /CAS | Control | Output | TTL, active low | DRAM Column Address Strobe output. |
| 13 | Z6 | Address Bus | Output | TTL | Multiplexed DRAM address bit 6. |
| 14 | Z5 | Address Bus | Output | TTL | Multiplexed DRAM address bit 5. |
| 15 | Z4 | Address Bus | Output | TTL | Multiplexed DRAM address bit 4. |
| 16 | Z3 | Address Bus | Output | TTL | Multiplexed DRAM address bit 3. |
| 17 | Z2 | Address Bus | Output | TTL | Multiplexed DRAM address bit 2. |
| 18 | Z1 | Address Bus | Output | TTL | Multiplexed DRAM address bit 1. |
| 19 | Z0 | Address Bus | Output | TTL | Multiplexed DRAM address bit 0. |
| 20 | GND | Ground | Power | 0 V | System ground (0 V). Note: the MC6883 runs very warm in normal operation! |
| 21 | A0 | Address Bus | Input | TTL | CPU Address bit 0 (also sets/clears SAM control register bits at $FFC0-$FFDF: Even = Clear, Odd = Set!). |
| 22 | A1 | Address Bus | Input | TTL | CPU Address bit 1. |
| 23 | A2 | Address Bus | Input | TTL | CPU Address bit 2. |
| 24 | A3 | Address Bus | Input | TTL | CPU Address bit 3. |
| 25 | A4 | Address Bus | Input | TTL | CPU Address bit 4. |
| 26 | A5 | Address Bus | Input | TTL | CPU Address bit 5. |
| 27 | A6 | Address Bus | Input | TTL | CPU Address bit 6. |
| 28 | A7 | Address Bus | Input | TTL | CPU Address bit 7. |
| 29 | Z7 (/RAS1) | Address Bus | Output | TTL | Multiplexed DRAM address bit 7 (for 64 KB 4164 DRAMs) OR second-bank /RAS1. |
| 30 | /RAS0 | Control | Output | TTL, active low | Primary DRAM Row Address Strobe. |
| 31 | A8 | Address Bus | Input | TTL | CPU Address bit 8. |
| 32 | A9 | Address Bus | Input | TTL | CPU Address bit 9. |
| 33 | A10 | Address Bus | Input | TTL | CPU Address bit 10. |
| 34 | A11 | Address Bus | Input | TTL | CPU Address bit 11. |
| 35 | E | Clock / Timing | Output | TTL clock | 6809E Enable (E) clock output (0.895 MHz normal, 1.79 MHz fast mode). |
| 36 | Q | Clock / Timing | Output | TTL clock | 6809E Quadrature (Q) clock output (leads E by 90 degrees). |
| 37 | VCLK | Clock / Timing | Output | TTL 3.58 MHz | 3.579545 MHz video clock output to MC6847 Pin 33. |
| 38 | A14 | Address Bus | Input | TTL | CPU Address bit 14. |
| 39 | A13 | Address Bus | Input | TTL | CPU Address bit 13. |
| 40 | VCC (+5V) / A15 | Power | Power | +5 V (A12 on internal mux) | +5 V supply (note: A15 and A12 are located on adjacent pins on some schematic conventions; Pin 40 is +5 V VCC). |
Common uses and repair diagnostics
The Motorola MC6883 (also badged Texas Instruments SN74LS783) Synchronous Address Multiplexer (SAM) is the master timing, DRAM controller, and memory-map decoder chip in the Dragon 32, Dragon 64, and Tandy Color Computer 1 and 2. Driven by a 14.31818 MHz crystal, it generates the 3.58 MHz VDG clock, the 0.895 MHz (or 1.79 MHz double-speed) E and Q quadrature clocks for the 6809E CPU, interleaves CPU and MC6847 VDG access to the 4116/4164 DRAM with zero bus contention, and outputs a 3-bit device select code (S0-S2 to a 74LS138) that maps the entire 64 KB address space!
Used in every Dragon 32, Dragon 64, Dragon 200-E, Tandy TRS-80 Color Computer 1, and Color Computer 2. Notably, the MC6883 has no data bus pins at all: to program its 16 internal control bits (VDG mode, video base address, 32K/64K Map Type, and 0.89/1.79 MHz CPU speed), the 6809E simply writes ANY value to an even address (to clear a bit) or odd address (to set a bit) between $FFC0 and $FFDF!
- If a Dragon 32/64 or CoCo 1/2 has a completely dead black screen with no CPU clocks, probe Pin 35 (E), Pin 36 (Q), and Pin 37 (VCLK). If 14.318 MHz is present on Pin 1/2 but E/Q/VCLK are dead, the MC6883 SAM has failed.
- The bipolar/NMOS MC6883 / SN74LS783 runs very hot (~60 C) in normal use — adding a 40-pin heatsink dramatically extends its lifespan.