Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | VPP | Power | Power | +5 V (read) or +12.5 V / +21 V (program) | Programming voltage. In normal read operation tie to VCC (+5 V). Only goes to +12.5 V (2764A) or +21 V (older 2764) while being programmed. Must NOT be left floating — a floating VPP is the usual reason a freshly socketed EPROM reads as garbage. On the 6264 SRAM this pin is no-connect. |
| 2 | A12 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 12. A12 is alone on pin 2, then A7 down to A0 descend on pins 3-10. |
| 3 | A7 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 7. The main address block descends: A7, A6, A5, A4, A3, A2, A1, A0 on pins 3-10. |
| 4 | A6 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 6. |
| 5 | A5 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 5. |
| 6 | A4 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 4. |
| 7 | A3 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 3. |
| 8 | A2 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 2. |
| 9 | A1 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 1. |
| 10 | A0 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 0. |
| 11 | D0 | Data Bus | Tri-state output | TTL, 0 V / 5 V, tri-state | Data bit 0. Tri-state outputs in read mode. The data bus is split either side of the ground pin: D0-D2 on 11-13, GND on 14, D3-D7 on 15-19. |
| 12 | D1 | Data Bus | Tri-state output | TTL, 0 V / 5 V, tri-state | Data bit 1. |
| 13 | D2 | Data Bus | Tri-state output | TTL, 0 V / 5 V, tri-state | Data bit 2. |
| 14 | GND | Ground | Power | 0 V | Ground. The data bus splits either side of this pin. |
| 15 | D3 | Data Bus | Tri-state output | TTL, 0 V / 5 V, tri-state | Data bit 3. |
| 16 | D4 | Data Bus | Tri-state output | TTL, 0 V / 5 V, tri-state | Data bit 4. |
| 17 | D5 | Data Bus | Tri-state output | TTL, 0 V / 5 V, tri-state | Data bit 5. |
| 18 | D6 | Data Bus | Tri-state output | TTL, 0 V / 5 V, tri-state | Data bit 6. |
| 19 | D7 | Data Bus | Tri-state output | TTL, 0 V / 5 V, tri-state | Data bit 7. |
| 20 | /CE | Control | Input | TTL, active low | Active low. Chip Enable. Low powers the chip up. On the 6264 SRAM this pin is /CS1 (same role). Using /CE as the select and leaving /OE low works, but cycling /CE instead of /OE is what gives CMOS versions their standby saving. |
| 21 | A10 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 10. The upper address bits are scattered: A10 (21), A11 (23), A9 (24), A8 (25). |
| 22 | /OE | Control | Input | TTL, active low | Active low. Output Enable. Low drives the data bus. Identical pin on the 6264 SRAM. |
| 23 | A11 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 11. |
| 24 | A9 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 9. |
| 25 | A8 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 8. |
| 26 | NC | No Connect | Not connected | No connect | No connect. On the 6264 SRAM this pin is CS2 (active-high chip select) — one of the four pin differences. |
| 27 | /PGM | Control | Input | TTL, active low | Active low. Program strobe. Tied high for reading; pulsed low with VPP at programming voltage to write. On the 6264 SRAM this pin is /WE (write enable). |
| 28 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The 2764 is an 8192-word x 8-bit UV-erasable EPROM in the JEDEC 28-pin byte-wide package. The most useful fact about this part is that the 2764 and the 6264 SRAM are the same pinout except for four pins — see the side-by-side list below. The trap is VPP (pin 1): it must not be left floating. In normal read operation it is tied to VCC (+5 V). It only goes to the programming voltage (+12.5 V on the 2764A, 21 V on older 2764 parts) while being programmed. Getting this wrong is the usual reason a freshly socketed EPROM reads as garbage.
The 2764 is an 8192-word x 8-bit UV-erasable EPROM in the JEDEC 28-pin byte-wide package. Erased by UV through the quartz window for about 20 minutes; opaque-topped parts are one-time-programmable or are 27C64 CMOS versions. A "blank" EPROM reads as all FF.
The most useful fact about this part is that the 2764 and the 6264 SRAM are the same pinout except for four pins: - pin 1: VPP on the 2764, no-connect on the 6264 - pin 20: /CE on the 2764, /CS1 on the 6264 (same role) - pin 26: no-connect on the 2764, CS2 on the 6264 - pin 27: /PGM on the 2764, /WE on the 6264 Everything else — all 13 address lines, all 8 data lines, GND, VCC and /OE — is identical. That is why ROM-to-RAM and EPROM-to-EPROM adapters are so simple, and why a 27128 or 27256 is a near drop-in with one extra address line each.
VPP (pin 1) must not be left floating. In normal read operation it is tied to VCC (+5 V). It only goes to the programming voltage (+12.5 V on the 2764A, 21 V on older 2764 parts) while being programmed. Getting this wrong is the usual reason a freshly socketed EPROM reads as garbage. /PGM (27) is also tied high for reading. /CE (20) low powers the chip up and /OE (22) low drives the data bus; using /CE as the select and leaving /OE low works, but cycling /CE instead of /OE is what gives CMOS versions their standby saving. The data pins are tri-state outputs in read mode, split either side of the ground pin exactly as on the 6264: D0-D2 on 11-13, GND on 14, D3-D7 on 15-19.
Commodore compatibility note: the C64 and original 1541 use 24-pin mask ROMs (2364 and 2332), which are NOT pin compatible with a 28-pin 2764. Replacing a C64 BASIC or KERNAL ROM with a 2764 needs a socket adapter. The 1541's 8 KB DOS ROM is a 2764 equivalent, and 16 KB ROMs map to a 27128.
- Check VPP (pin 1) and /PGM (pin 27) are at +5 V, not floating. A floating VPP is the usual reason a freshly socketed EPROM reads as garbage.
- Confirm /CE (pin 20) and /OE (pin 22) are being driven. /CE low powers the chip, /OE low drives the bus.
- Read the device in a programmer and checksum it against a known good dump — that is the only reliable test.
- A partially failed EPROM ("bit rot", common in 40-year-old parts) reads consistently but with a wrong checksum, so a clean-looking read proves nothing without the comparison.
- A blank EPROM reads as all FF — if you see all FF, the chip may be unprogrammed or erased.