Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | VSS | Ground | Power | 0 V | Ground. The 6502 has TWO ground pins (1 and 21); a continuity check on one does not prove the other. |
| 2 | RDY | Control | Input | TTL | Ready. Pulled low by slow memory to stretch the current read cycle; the CPU waits until it returns high. |
| 3 | PHI1 | Clock / Timing | Output | TTL clock | Phase 1 clock output. Derived from the PHI0 input on pin 37; the inverse of PHI2. |
| 4 | /IRQ | Control | Input | TTL, active low | Active low. Maskable interrupt request. Serviced at the end of the current instruction if the interrupt flag is clear. |
| 5 | NC | No Connect | Not connected | No connect | No connect on the NMOS 6502. The CMOS W65C02S reuses this pin, so a board that grounds or pulls it may not accept a W65C02S as a drop-in. |
| 6 | /NMI | Control | Input | TTL, active low | Active low. Non-maskable interrupt. Always serviced; the CPU fetches the NMI vector. |
| 7 | SYNC | Control | Output | TTL, 0 V / 5 V | Synchronise. Goes high during an opcode fetch — the classic way to prove the CPU is actually executing rather than just toggling the bus. |
| 8 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. |
| 9 | A0 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 0. |
| 10 | A1 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 1. |
| 11 | A2 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 2. |
| 12 | A3 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 3. |
| 13 | A4 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 4. |
| 14 | A5 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 5. |
| 15 | A6 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 6. |
| 16 | A7 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 7. |
| 17 | A8 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 8. |
| 18 | A9 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 9. |
| 19 | A10 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 10. |
| 20 | A11 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 11. |
| 21 | VSS | Ground | Power | 0 V | Second ground pin. Both pin 1 and pin 21 must be tied to 0 V; a continuity check on one does not prove the other. |
| 22 | A12 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 12. |
| 23 | A13 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 13. |
| 24 | A14 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 14. |
| 25 | A15 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 15, the most significant address line. |
| 26 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 7. The data bus DESCENDS: D7 here at pin 26 down to D0 at pin 33 — the single most common wiring mistake on a breadboarded 6502. |
| 27 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 6. |
| 28 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 5. |
| 29 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 4. |
| 30 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 3. |
| 31 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 2. |
| 32 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 1. |
| 33 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 0. |
| 34 | R/W | Control | Output | TTL, 0 V / 5 V | Read / Write. High during a read, low during a write. |
| 35 | NC | No Connect | Not connected | No connect | No connect on the NMOS 6502; reused on the CMOS W65C02S. |
| 36 | NC | No Connect | Not connected | No connect | No connect on the NMOS 6502; reused on the CMOS W65C02S. |
| 37 | PHI0 | Clock / Timing | Input | TTL clock | Phase 0 clock INPUT. Some sources label this pin 'phi 2 in'; all bus timing is derived from it. No clock here is a board fault, not a CPU fault. |
| 38 | /SO | Control | Input | TTL, active low | Active low. Set overflow. A negative edge sets the overflow flag; usually tied high and forgotten. |
| 39 | PHI2 | Clock / Timing | Output | TTL clock | Phase 2 clock output. The main system clock derived from PHI0; used to time all bus access. |
| 40 | /RES | Control | Input | TTL, active low | Active low. Reset. Held low on power-up to force the CPU to fetch the reset vector. |
Common uses and repair diagnostics
The MOS 6502 is the 8-bit CPU that drove the Apple II, the Commodore PET and VIC-20, the BBC Micro, the Atari 2600 and 800, and the NES as the 2A03 derivative. It presents a 16-bit address bus, an 8-bit bidirectional data bus and a single clock input, and its simple, static design made it the cheapest microprocessor of its generation. The 6510 and 8501 are 6502-core derivatives with extra I/O ports, but they are NOT pin-compatible with the 6502 — the pin assignments shift, and the three cannot be swapped.
The 6502 sits at the centre of the Apple II, the Commodore PET and VIC-20, the BBC Micro, the Atari 2600 and 800, and the NES. Its 16-bit address bus decodes straight into 64 KB of memory, its single clock input keeps the board simple, and its SYNC output lets a logic probe confirm the CPU is fetching opcodes rather than just toggling pins. The 6510 and 8501 are 6502-core parts with an added I/O port, but neither is pin-compatible — the pin assignments shift, so the three cannot be substituted for one another.
On the bench a dead 6502 usually shows up as a stuck address bus. Probe PHI0 (pin 37) first: no clock is a board fault, not a CPU fault. Check both VSS pins (1 and 21) for a solid ground, since a continuity check on one does not prove the other. The standard free-run test — lift D0 to D7, tie the bus to $EA (NOP), and watch A0 to A15 count up cleanly — is the surest way to prove a 6502 is alive without any other chip on the board.
- Scope pin 37 (PHI0) for a clean clock at the rated speed. No clock here is a board fault, not a CPU fault.
- Check pin 8 (VCC) at 5 V and BOTH pin 1 and pin 21 (VSS) at 0 V; a continuity check on one ground does not prove the other.
- Probe pin 7 (SYNC) during reset; it should pulse high on each opcode fetch, proving the CPU is executing.
- Hold pin 40 (/RES) low, then release; the CPU should fetch from the reset vector, driving the address bus and R/W.
- Free-run test: lift D0 to D7, tie the bus to $EA (NOP), and watch A0 to A15 count up cleanly — the standard proof a 6502 is alive.