Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | VSS | Ground | Power | 0 V | Ground. VCC is pin 20, NOT pin 40. Pin 40 is CA1, an input — 5 V here will damage the chip. |
| 2 | PA0 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 0. Independently programmable as input or output. |
| 3 | PA1 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 1. |
| 4 | PA2 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 2. |
| 5 | PA3 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 3. |
| 6 | PA4 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 4. |
| 7 | PA5 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 5. |
| 8 | PA6 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 6. |
| 9 | PA7 | I/O | Bidirectional | TTL, 0 V / 5 V | Port A bit 7. |
| 10 | PB0 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 0. Independently programmable as input or output. |
| 11 | PB1 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 1. |
| 12 | PB2 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 2. |
| 13 | PB3 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 3. |
| 14 | PB4 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 4. |
| 15 | PB5 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 5. |
| 16 | PB6 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 6. |
| 17 | PB7 | I/O | Bidirectional | TTL, 0 V / 5 V | Port B bit 7. |
| 18 | CB1 | I/O | Input | TTL | Port B control line 1. INPUT ONLY — unlike the 6522, where CB1 is bidirectional because it doubles as the shift-register clock. This differs from the 6522. |
| 19 | CB2 | I/O | Bidirectional | TTL | Port B control line 2. Bidirectional handshake or pulse output. |
| 20 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. This is pin 20, not pin 40. |
| 21 | R/W | Control | Input | TTL | Read / Write. High reads a register, low writes one. The internal slash is NOT an active-low marker. |
| 22 | CS0 | Control | Input | TTL, active high | Chip select 0. ACTIVE HIGH. All three selects must be satisfied: CS0 high, CS1 high, /CS2 low. |
| 23 | /CS2 | Control | Input | TTL, active low | Active low. Chip select 2. All three selects must be satisfied: CS0 (pin 22) high, CS1 (pin 24) high, /CS2 low. |
| 24 | CS1 | Control | Input | TTL, active high | Chip select 1. ACTIVE HIGH. All three selects must be satisfied: CS0 high, CS1 high, /CS2 (pin 23) low. Note the mixed polarity of the three selects. |
| 25 | E | Clock / Timing | Input | TTL clock | Enable clock. The 6800 bus enable clock for register access. All register access is timed to this clock. |
| 26 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 7. |
| 27 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 6. |
| 28 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 5. |
| 29 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 4. |
| 30 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 3. |
| 31 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 2. |
| 32 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 1. |
| 33 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 0. |
| 34 | /RESET | Control | Input | TTL, active low | Active low. Reset. Clears all registers and sets all port lines to input. |
| 35 | RS1 | Address Bus | Input | TTL | Register select bit 1. RS0 (pin 36) and RS1 select one of four register addresses. Note RS1 is on the LOWER pin number (35) and RS0 on 36 — they descend. |
| 36 | RS0 | Address Bus | Input | TTL | Register select bit 0. |
| 37 | /IRQB | Control | Open-drain / open-collector | TTL, active low, open drain | Active low. Interrupt request for port B, open-drain. Can share a pull-up with /IRQA (pin 38) or other open-drain interrupt sources. |
| 38 | /IRQA | Control | Open-drain / open-collector | TTL, active low, open drain | Active low. Interrupt request for port A, open-drain. Two separate interrupt outputs, one per port — unlike the 6522, which has a single /IRQ. |
| 39 | CA2 | I/O | Bidirectional | TTL | Port A control line 2. Bidirectional handshake or pulse output. |
| 40 | CA1 | I/O | Input | TTL | Port A control line 1. INPUT ONLY — unlike CA2, CB2, this pin cannot be an output. Do not put 5 V here; it is not VCC. |
Common uses and repair diagnostics
The Motorola MC6821 PIA (Peripheral Interface Adapter) gives a 6800-family CPU two 8-bit bidirectional ports. The MOS 6520 is Commodore's version of the same part and is interchangeable. Note the supply pins: VSS is pin 1 and VCC is pin 20 — NOT pin 40. Pin 40 is CA1, an input. This is the 6800-family convention shared with the 6522 VIA, the 6526 CIA, the 6845 CRTC and the 6850 ACIA in this library — putting 5 V on pin 40 will damage any of them.
The MC6821 PIA is the 6800-family peripheral chip. Two 8-bit ports, two interrupt outputs and a clean register model cover most glue-logic needs. The MOS 6520 is Commodore's version of the same part and is interchangeable. Used in the Apple II (the 6520 on early boards), the Commodore PET, the Dragon 32/64, the Tandy CoCo (two of them) and countless 6800 industrial boards.
Pins 1 to 20 are IDENTICAL to the 6522 VIA and the 6526 CIA: VSS, PA0-PA7, PB0-PB7, CB1, CB2, VCC. The three parts diverge only from pin 21 onwards. That half-shared pinout is useful to know and dangerous to assume — none of them substitute for another. The supply trap is the same: VCC is pin 20, not pin 40. Pin 40 is CA1, an input — 5 V here will damage the chip.
Three chip selects with mixed polarity: CS0 (pin 22) and CS1 (pin 24) active HIGH, /CS2 (pin 23) active LOW. All three must be satisfied together. Two separate interrupt outputs, /IRQA (pin 38) and /IRQB (pin 37), one per port, both open-drain so they can share a pull-up. CA1 (pin 40) and CB1 (pin 18) are INPUT ONLY; CA2 (pin 39) and CB2 (pin 19) are bidirectional. This differs from the 6522, where CB1 is bidirectional because it doubles as the shift-register clock. Only two register-select lines, RS0 (pin 36) and RS1 (pin 35) — four addresses, versus the 6522's sixteen. Note RS1 is on the LOWER pin number (35) and RS0 on 36, i.e. they descend.
- Check pin 1 (VSS) at 0 V and pin 20 (VCC) at 5 V. Do NOT expect VCC at pin 40 — that is CA1, an input.
- Write $FF to a data direction register and confirm all eight port pins can be driven high and low. A port bit that will not change state, or that reads back a different value from what was written, points at the PIA.
- Because the port pins drive external hardware directly they are the usual casualty of a wiring fault, so check for a short on the board before condemning the chip.
- CA1 (pin 40) and CB1 (pin 18) are input-only. Do not try to drive them as outputs.
- All three chip selects must be satisfied: CS0 (pin 22) high, CS1 (pin 24) high, /CS2 (pin 23) low. A stuck select line will prevent register access.