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MOS 8372A / 8375 Fat Agnus Pinout — Amiga DMA, Blitter & Copper Chip (PLCC-84)

PLCC-84 · Sound & Video · MOS 8370 / 8371 / 8372A / 8375 (PLCC-84)

Pinout diagram

Used in Retro Machine Hubs

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[Amiga Hub — Amiga (A500 / A600 / A1200)] [Big-Box Amiga Hub — Big-Box Amiga (A1000–A4000)]

Summary specifications

Technology HMOS-2
Operating Voltage +5 V +/-5% (VCC pin 19, GND pins 1, 53 and 73)
Clock Input 28.37516 MHz (PAL) / 28.63636 MHz (NTSC) on Pin 34 (28MHZ)
Chip RAM Capacity 512 KB (8370/8371), 1 MB (8372A), or 2 MB (8372B / 8375)
PAL / NTSC Pin 41 On 8372A, Pin 41 selects PAL (Low = 0 V) vs NTSC (High = +5 V)!
WARNING 8375 (318069-xx / 390544-xx) is NOT pin-compatible with 8370/8372A without an adapter!

Full pin reference

Pin Name Group Direction Levels Description
1 VSS1 Ground Power 0 V Primary digital ground.
2 DRD12 Data Bus Bidirectional TTL Chip RAM Data bus bit 12.
3 DRD11 Data Bus Bidirectional TTL Chip RAM Data bus bit 11.
4 DRD10 Data Bus Bidirectional TTL Chip RAM Data bus bit 10.
5 DRD9 Data Bus Bidirectional TTL Chip RAM Data bus bit 9.
6 DRD8 Data Bus Bidirectional TTL Chip RAM Data bus bit 8.
7 DRD7 Data Bus Bidirectional TTL Chip RAM Data bus bit 7.
8 DRD6 Data Bus Bidirectional TTL Chip RAM Data bus bit 6.
9 DRD5 Data Bus Bidirectional TTL Chip RAM Data bus bit 5.
10 DRD4 Data Bus Bidirectional TTL Chip RAM Data bus bit 4.
11 DRD3 Data Bus Bidirectional TTL Chip RAM Data bus bit 3.
12 DRD2 Data Bus Bidirectional TTL Chip RAM Data bus bit 2.
13 DRD1 Data Bus Bidirectional TTL Chip RAM Data bus bit 1.
14 DRD0 Data Bus Bidirectional TTL Chip RAM Data bus bit 0 (LSB).
15 A1 Address Bus Input TTL CPU Address bit 1.
16 A2 Address Bus Input TTL CPU Address bit 2.
17 A3 Address Bus Input TTL CPU Address bit 3.
18 A4 Address Bus Input TTL CPU Address bit 4.
19 VCC (+5V) Power Power +5 V Main +5 V power supply.
20 A5 Address Bus Input TTL CPU Address bit 5.
21 A6 Address Bus Input TTL CPU Address bit 6.
22 A7 Address Bus Input TTL CPU Address bit 7.
23 A8 Address Bus Input TTL CPU Address bit 8.
24 A9 Address Bus Input TTL CPU Address bit 9.
25 A10 Address Bus Input TTL CPU Address bit 10.
26 A11 Address Bus Input TTL CPU Address bit 11.
27 A12 Address Bus Input TTL CPU Address bit 12.
28 A13 Address Bus Input TTL CPU Address bit 13.
29 A14 Address Bus Input TTL CPU Address bit 14.
30 A15 Address Bus Input TTL CPU Address bit 15.
31 A16 Address Bus Input TTL CPU Address bit 16.
32 A17 Address Bus Input TTL CPU Address bit 17.
33 A18 Address Bus Input TTL CPU Address bit 18.
34 28MHZ Clock / Timing Input TTL 28 MHz 28.375 MHz (PAL) / 28.636 MHz (NTSC) master oscillator input.
35 A19 Address Bus Input TTL CPU Address bit 19 (used for 1 MB Chip RAM on 8372A — JP2 on A500 Rev 6A!).
36 /XCLKEN Control Input TTL External Genlock Clock Enable.
37 CDAC Clock / Timing Output TTL 7 MHz 7.09 MHz shifted clock output.
38 7MHZ Clock / Timing Output TTL 7.09 MHz Master 7.09 MHz (PAL) / 7.16 MHz (NTSC) 68000 CPU clock output!
39 CCKQ Clock / Timing Output TTL 3.55 MHz Colour Clock Quadrature output (3.55 MHz) to Denise and Paula.
40 CCK Clock / Timing Output TTL 3.55 MHz Master Colour Clock output (3.55 MHz) to Denise, Paula and Gary.
41 TEST (PAL/NTSC) Control Input TTL On 8372A ECS Agnus: Ground (0 V) = PAL 50 Hz; High (+5 V) = NTSC 60 Hz!
42 /RST Control Input TTL, active low System Reset input.
43 /CSYNC I/O Bidirectional TTL, active low Composite Sync output (or Genlock sync input).
44 /VSYNC I/O Bidirectional TTL, active low Vertical Sync (50/60 Hz — also feeds CIA-A TOD tick on A500).
45 /HSYNC I/O Bidirectional TTL, active low Horizontal Sync (15.6 kHz).
46 /BLISS Control Output TTL, active low Blitter Slowdown — tells Gary when the Blitter is hogging the Chip RAM bus.
47 /busWR (/WE) Control Output TTL, active low Chip RAM Write Enable output.
48 PRW Control Input TTL Processor Read/Write from Gary.
49 /REGEN Control Input TTL, active low Custom Chip Register Enable ($DFF000-$DFF1FF) from Gary.
50 /AS Control Input TTL, active low Address Strobe input.
51 /RAMEN Control Input TTL, active low Chip RAM Enable input from Gary.
52 RGA8 Address Bus Output TTL Register Address Bus bit 8 (commands Denise & Paula every colour clock).
53 VSS2 Ground Power 0 V Ground.
54 RGA7 Address Bus Output TTL Register Address Bus bit 7.
55 RGA6 Address Bus Output TTL Register Address Bus bit 6.
56 RGA5 Address Bus Output TTL Register Address Bus bit 5.
57 RGA4 Address Bus Output TTL Register Address Bus bit 4.
58 RGA3 Address Bus Output TTL Register Address Bus bit 3.
59 RGA2 Address Bus Output TTL Register Address Bus bit 2.
60 RGA1 Address Bus Output TTL Register Address Bus bit 1 (LSB).
61 DMAL Control Input TTL DMA Request Line serial stream from Paula (requests audio and floppy DMA slots from Agnus!).
62 DRA0 Address Bus Output TTL Multiplexed Chip RAM address bit 0.
63 DRA1 Address Bus Output TTL Multiplexed Chip RAM address bit 1.
64 DRA2 Address Bus Output TTL Multiplexed Chip RAM address bit 2.
65 DRA3 Address Bus Output TTL Multiplexed Chip RAM address bit 3.
66 DRA4 Address Bus Output TTL Multiplexed Chip RAM address bit 4.
67 DRA5 Address Bus Output TTL Multiplexed Chip RAM address bit 5.
68 DRA6 Address Bus Output TTL Multiplexed Chip RAM address bit 6.
69 DRA7 Address Bus Output TTL Multiplexed Chip RAM address bit 7.
70 DRA8 Address Bus Output TTL Multiplexed Chip RAM address bit 8.
71 /LDS (/CASL) Control Input TTL, active low Lower Data Strobe input (drives Lower Byte /CASL).
72 /UDS (/CASU) Control Input TTL, active low Upper Data Strobe input (drives Upper Byte /CASU).
73 VSS3 Ground Power 0 V Ground.
74 /CASL Control Output TTL, active low Chip RAM Lower Byte Column Address Strobe.
75 /CASU Control Output TTL, active low Chip RAM Upper Byte Column Address Strobe.
76 /RAS1 Control Output TTL, active low Chip RAM Bank 1 Row Address Strobe (second 512 KB bank on trapdoor / motherboard — JP7A cut on 1MB Chip RAM mod!).
77 /RAS0 Control Output TTL, active low Chip RAM Bank 0 Row Address Strobe (first 512 KB bank).
78 /LPEN I/O Input TTL, active low Light Pen trigger input (from Joystick port Pin 6).
79 DRA9 Address Bus Output TTL Multiplexed Chip RAM address bit 9 (present on 8372B / 8375 for 2 MB Chip RAM!).
80 /BERR Control Input TTL Bus Error / External clock input.
81 DRD15 Data Bus Bidirectional TTL Chip RAM Data bus bit 15 (MSB).
82 DRD14 Data Bus Bidirectional TTL Chip RAM Data bus bit 14.
83 DRD13 Data Bus Bidirectional TTL Chip RAM Data bus bit 13.
84 NC / XCLK Clock / Timing Input TTL External Genlock clock input.

Common uses and repair diagnostics

Named after 'Address Generator', the 84-pin PLCC Fat Agnus (8370 NTSC / 8371 PAL 512 KB in Rev 5 A500 & Rev 4 A2000; 8372A 1 MB ECS in Rev 6A A500 & Rev 6 A2000; 8372B/8375 2 MB ECS in A500+, A600 & A3000) is the heart of the Commodore Amiga chipset. It contains the 25-channel DMA controller (feeding bitplanes, sprites, audio, and floppy disk without CPU intervention), the hardware Blitter (high-speed block image transfer & line draw engine), the Copper (scanline-synchronized co-processor), the Chip RAM /RAS and /CAS refresh multiplexer (DRA0-DRA9), and the 8-bit Register Address Bus (RGA1-RGA8) that commands Denise and Paula on every 280 ns colour clock!

Used in the Amiga 500, A500+, A600, A2000, A3000, and CDTV. The #1 cause of a Green Boot Screen (Chip RAM Error) on an Amiga 500 or A2000 is tarnished J-lead contacts or a cracked corner on the brown 84-pin PLCC Fat Agnus socket!

  • NEVER pry Fat Agnus out of its 84-pin PLCC socket with a flathead screwdriver — you will crack the brittle plastic socket corner! Always use a proper 2-hook PLCC extractor tool.
  • Green Boot Screen on an A500/A2000: extract Fat Agnus with a PLCC puller, clean all 84 J-leads and socket pins with DeoxIT D5, gently tension the corner pins inward with a dental pick, and reseat.
  • On an 8372A ECS Agnus (Rev 6A A500 / Rev 6.2 A2000), grounding or lifting Pin 41 switches the machine between PAL (50 Hz) and NTSC (60 Hz)!

Datasheets and references

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