Pinout diagram
Used in Retro Machine Hubs
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Summary specifications
Technology
HMOS-2
Operating Voltage
+5 V +/-5% (VCC pin 1, VSS pin 25)
Register Addresses
$D500-$D50B (always visible in I/O block) and $FF00-$FF04 (always visible in all banks!)
RAM Banking
/CAS0 (Pin 32, Bank 0 64KB) and /CAS1 (Pin 31, Bank 1 64KB)
CPU Handshake
Pin 43 (/Z80EN) switches active CPU between Z80A and 8502
Mode Sense Inputs
Pin 44 (/EXROM), Pin 45 (/GAME), Pin 47 (40/80 Display Key)
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | VCC (+5V) | Power | Power | +5 V | Main +5 V supply. |
| 2 | /RESET | Control | Input | TTL, active low | System Reset input (forces Z80 active and Bank 0 ROM enabled on cold boot). |
| 3 | TA15 | Address Bus | Output | TTL | Translated Address bit 15 (feeds PLA and DRAM multiplexers). |
| 4 | TA14 | Address Bus | Output | TTL | Translated Address bit 14. |
| 5 | TA13 | Address Bus | Output | TTL | Translated Address bit 13. |
| 6 | TA12 | Address Bus | Output | TTL | Translated Address bit 12. |
| 7 | TA11 | Address Bus | Output | TTL | Translated Address bit 11. |
| 8 | TA10 | Address Bus | Output | TTL | Translated Address bit 10. |
| 9 | TA9 | Address Bus | Output | TTL | Translated Address bit 9. |
| 10 | TA8 | Address Bus | Output | TTL | Translated Address bit 8 (allows Zero-Page $0000 and Stack $0100 to be remapped to any page!). |
| 11 | A15 | Address Bus | Input | TTL | CPU Address bit 15. |
| 12 | A14 | Address Bus | Input | TTL | CPU Address bit 14. |
| 13 | A13 | Address Bus | Input | TTL | CPU Address bit 13. |
| 14 | A12 | Address Bus | Input | TTL | CPU Address bit 12. |
| 15 | A11 | Address Bus | Input | TTL | CPU Address bit 11. |
| 16 | A10 | Address Bus | Input | TTL | CPU Address bit 10. |
| 17 | A9 | Address Bus | Input | TTL | CPU Address bit 9. |
| 18 | A8 | Address Bus | Input | TTL | CPU Address bit 8. |
| 19 | A7 | Address Bus | Input | TTL | CPU Address bit 7. |
| 20 | A6 | Address Bus | Input | TTL | CPU Address bit 6. |
| 21 | A5 | Address Bus | Input | TTL | CPU Address bit 5. |
| 22 | A4 | Address Bus | Input | TTL | CPU Address bit 4. |
| 23 | A3 | Address Bus | Input | TTL | CPU Address bit 3. |
| 24 | A2 | Address Bus | Input | TTL | CPU Address bit 2. |
| 25 | VSS | Ground | Power | 0 V | System ground (0 V). |
| 26 | A1 | Address Bus | Input | TTL | CPU Address bit 1. |
| 27 | A0 | Address Bus | Input | TTL | CPU Address bit 0. |
| 28 | MUX | Control | Input | TTL | DRAM address multiplexer timing input from PLA. |
| 29 | PHI0 | Clock / Timing | Input | TTL clock | System clock input. |
| 30 | R/W | Control | Input | TTL | Read/Write input. |
| 31 | /CAS1 | Control | Output | TTL, active low | Column Address Strobe for RAM Bank 1 (Upper 64 KB DRAMs U46-U53). |
| 32 | /CAS0 | Control | Output | TTL, active low | Column Address Strobe for RAM Bank 0 (Lower 64 KB DRAMs U38-U45). |
| 33 | D0 | Data Bus | Bidirectional | TTL | Data bus bit 0. |
| 34 | D1 | Data Bus | Bidirectional | TTL | Data bus bit 1. |
| 35 | D2 | Data Bus | Bidirectional | TTL | Data bus bit 2. |
| 36 | D3 | Data Bus | Bidirectional | TTL | Data bus bit 3. |
| 37 | D4 | Data Bus | Bidirectional | TTL | Data bus bit 4. |
| 38 | D5 | Data Bus | Bidirectional | TTL | Data bus bit 5. |
| 39 | D6 | Data Bus | Bidirectional | TTL | Data bus bit 6. |
| 40 | D7 | Data Bus | Bidirectional | TTL | Data bus bit 7. |
| 41 | AEC | Control | Input | TTL | Address Enable Control input. |
| 42 | /MMUCS | Control | Input | TTL, active low | MMU Chip Select ($D500-$D50B from PLA). |
| 43 | /Z80EN | Control | Output | TTL, active low | Z80 Enable output (Low at reset = Z80A runs; High after Z80 boot check = 8502 runs!). |
| 44 | /EXROM | I/O | Bidirectional | TTL, active low | Cartridge /EXROM sense & C64 mode output. |
| 45 | /GAME | I/O | Bidirectional | TTL, active low | Cartridge /GAME sense & C64 mode output. |
| 46 | FSDIR | I/O | Output | TTL | Fast Serial Direction output (controls 1571/1581 burst mode shift direction!). |
| 47 | 40/80 | I/O | Input | TTL | Reads the latching 40/80 DISPLAY keyboard switch ($D505 bit 7). |
| 48 | MS3 (C128/64) | Control | Output | TTL | Operating Mode Status output (0 = C128 mode, 1 = C64 mode). |
Common uses and repair diagnostics
Sitting in socket U7 of every Commodore 128 and C128D, the 48-pin MOS 8722 Memory Management Unit (MMU) is the conductor of the C128's three-personality architecture. At cold reset, the 8722 asserts /Z80EN (Pin 43) low so the Zilog Z80A boots first at 0000h to check for a CP/M boot disk or C64 cartridge (/GAME, /EXROM); the Z80 then writes to the MMU Mode Configuration Register ($D505) to hand the bus over to the MOS 8502! In C128 mode, the 8722 banks the two 64 KB DRAM banks via /CAS0 (Pin 32) and /CAS1 (Pin 31), creates shared common RAM at the bottom/top of memory, and translates A8-A15 into TA8-TA15 so Zero-Page ($00) and the 6502 Stack ($01) can be relocated anywhere in the 128 KB RAM!
Used exclusively in socket U7 of the Commodore 128, C128D, and C128DCR.
- Black screen on a C128: probe Pin 43 (/Z80EN) during reset! At the instant of reset, Pin 43 must go LOW (0 V) for ~100 ms while the Z80 runs its boot check, and then snap HIGH (+5 V) to start the 8502. If Pin 43 stays stuck low (0 V), either the Z80A CPU, the Z80 BIOS ROM (U18), or the 8722 MMU has failed!
- Test if the C128 boots into C64 mode by grounding Cartridge Port Pin 8 (/GAME) at power-on.