Pinout diagram
Used in Retro Machine Hubs
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Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | ADD8 (DATA) | I/O | Bidirectional | MOS | Speech ROM address bit 8 output AND serial phrase data input from TMS6100 VSM ROM! |
| 2 | ADD2 | Address Bus | Output | MOS | Speech ROM nibble address bit 2. |
| 3 | ROMCLK | Clock / Timing | Output | MOS clock | 160 kHz clock output to TMS6100 / TMC0350 Phrase ROMs. |
| 4 | VDD (-5V) | Power | Power | -5 V | -5 V PMOS drain supply. |
| 5 | VSS (+5V) | Power | Power | +5 V | +5 V substrate/logic supply. |
| 6 | OSC | Clock / Timing | Input | RC clock | RC oscillator resistor/capacitor timing node (~640 kHz for 8 kHz sample rate). |
| 7 | T11 | Clock / Timing | Output | Clock sync | Internal timing sync output. |
| 8 | SPKR | Analog | Output | Analog audio | Analog speech audio output from internal 8-bit current DAC. |
| 9 | TEST | No Connect | Input | Factory test | Factory test pin (leave unconnected or tie to VSS). |
| 10 | /PROM OUT | I/O | Output | TTL | Optional strobe output. |
| 11 | VREF (GND) | Ground | Power | 0 V | 0 V Digital and Audio Reference Ground. |
| 12 | D0 (MSB) | Data Bus | Bidirectional | TTL | CPU Data bus bit 0 (MOST Significant Bit!). |
| 13 | D1 | Data Bus | Bidirectional | TTL | CPU Data bus bit 1. |
| 14 | D2 | Data Bus | Bidirectional | TTL | CPU Data bus bit 2. |
| 15 | M0 | Control | Output | MOS | Speech ROM Command bit 0 (00=Idle, 01=Read Bit, 10=Load Address). |
| 16 | M1 | Control | Output | MOS | Speech ROM Command bit 1. |
| 17 | /INT | Control | Output | TTL, active low | Interrupt output (asserts when FIFO drops below half-full or speech finishes). |
| 18 | /READY | Control | Output | TTL, active low | Ready handshake output (pauses CPU during slow internal register transfers; takes up to 10 us!). |
| 19 | D3 | Data Bus | Bidirectional | TTL | CPU Data bus bit 3. |
| 20 | D4 | Data Bus | Bidirectional | TTL | CPU Data bus bit 4. |
| 21 | ADD1 | Address Bus | Output | MOS | Speech ROM nibble address bit 1 (LSB). |
| 22 | ADD4 | Address Bus | Output | MOS | Speech ROM nibble address bit 4. |
| 23 | D5 | Data Bus | Bidirectional | TTL | CPU Data bus bit 5. |
| 24 | NC | No Connect | Not connected | NC | No connection. |
| 25 | D6 | Data Bus | Bidirectional | TTL | CPU Data bus bit 6. |
| 26 | /WS | Control | Input | TTL, active low | Write Select strobe input. |
| 27 | /RS | Control | Input | TTL, active low | Read Select strobe input. |
| 28 | D7 (LSB) | Data Bus | Bidirectional | TTL | CPU Data bus bit 7 (LEAST Significant Bit!). |
Common uses and repair diagnostics
Derived from Texas Instruments' Speak & Spell (TMS5100) chip, the 28-pin PMOS TMS5200 / TMC0285 and NMOS/CMOS TMS5220 / TMS5220C model the human vocal tract using a 10-stage Linear Predictive Coding (LPC-10) digital lattice filter! The host CPU can either command the TMS5220 to speak vocabulary words directly out of up to 16 serial Voice Synthesis Memory (VSM) phrase ROMs (TMC0350 / TMS6100, connected to Pins 1, 2, 3, 21, 22, 24 via a 4-bit multiplexed nibble bus!) OR stream custom LPC phoneme frames straight from CPU RAM through the on-chip 128-bit FIFO buffer ('Speak External' mode).
Used in the Texas Instruments PHP1500 Solid State Speech Synthesizer (for the TI-99/4A, using the TMC0285/TMS5200), the Acorn BBC Micro Speech Upgrade (IC99 TMS5220 + IC98 Kenneth Kendall TMS6100 PHROM), the Street Electronics Echo II (for the Apple II), and Atari/Bally arcade games (Star Wars, Firefox, Gauntlet, Indiana Jones, Discs of Tron).
- Verify both +5 V (Pin 5) and -5 V (Pin 4) relative to Ground (Pin 11) — if the -5 V rail is missing, the TMS5220 cannot run and holds /READY (Pin 18) stuck!
- Remember that on an 8-bit 6502 (BBC Micro / Apple II), D0 on the 6502 (LSB) must be wired to Pin 28 (D7 LSB) of the TMS5220 and D7 on the 6502 (MSB) to Pin 12 (D0 MSB)!