Pinout diagram
Used in Retro Machine Hubs
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Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | XTAL1 | Clock / Timing | Input | 16 MHz | 16.000 MHz crystal oscillator input. |
| 2 | XTAL2 | Clock / Timing | Output | 16 MHz | 16.000 MHz crystal oscillator output. |
| 3 | /M1 | Control | Input | TTL, active low | Z80 Machine Cycle 1 input (used with /IORQ to detect Interrupt Acknowledge and clear the 300 Hz raster counter). |
| 4 | PHI | Clock / Timing | Output | TTL 4 MHz | 4.0 MHz master CPU clock output to Z80 Pin 6. No clock here = dead Gate Array or crystal! |
| 5 | /RED | Analog | Output | 3-state ternary | Red video output (High, Low, or Hi-Z mid-level -> 3 brightness levels). |
| 6 | /GREEN | Analog | Output | 3-state ternary | Green video output (3 brightness levels). |
| 7 | /SYNC | Analog | Output | TTL, active low | Composite Video Sync output (to DIN-6 Monitor Pin 4). |
| 8 | /BLUE | Analog | Output | 3-state ternary | Blue video output (3 brightness levels). |
| 9 | D0 | Data Bus | Input | TTL | Data bus bit 0. |
| 10 | D1 | Data Bus | Input | TTL | Data bus bit 1. |
| 11 | D2 | Data Bus | Input | TTL | Data bus bit 2. |
| 12 | D3 | Data Bus | Input | TTL | Data bus bit 3. |
| 13 | D4 | Data Bus | Input | TTL | Data bus bit 4. |
| 14 | D5 | Data Bus | Input | TTL | Data bus bit 5. |
| 15 | D6 | Data Bus | Input | TTL | Data bus bit 6 (Gate Array I/O write register select when D7=0, D6=1). |
| 16 | D7 | Data Bus | Input | TTL | Data bus bit 7. |
| 17 | /CASAD | Control | Output | TTL | DRAM Column Address multiplexer select. |
| 18 | /MWE | Control | Output | TTL, active low | Memory Write Enable output to 4164 DRAMs. |
| 19 | HSYNC | Clock / Timing | Input | TTL | Horizontal Sync input from 6845 CRTC Pin 39 (clocks the Gate Array's 52-line /INT divider!). |
| 20 | CCLK | Clock / Timing | Output | TTL 1 MHz | 1.0 MHz Character Clock output to 6845 CRTC Pin 21. |
| 21 | /CPU | Control | Output | TTL | Multiplexer select between Z80 CPU address and 6845 CRTC video address. |
| 22 | VDD | Power | Power | +5 V | +5 V power supply. |
| 23 | /ROME | Control | Output | TTL, active low | ROM Enable output (asserted for Lower OS ROM $0000-$3FFF or Upper BASIC/AMSDOS ROM $C000-$FFFF). |
| 24 | /244E | Control | Output | TTL, active low | 74LS244 data bus buffer enable (isolates CPU data bus from DRAM during video fetches). |
| 25 | /CAS | Control | Output | TTL, active low | DRAM Column Address Strobe. |
| 26 | VSYNC | Clock / Timing | Input | TTL | Vertical Sync input from 6845 CRTC Pin 40. |
| 27 | DISPEN | Control | Input | TTL | Display Enable input from 6845 CRTC Pin 18 (switches between active screen pixels and BORDER colour). |
| 28 | /RD | Control | Input | TTL, active low | Z80 Read strobe input. |
| 29 | /MREQ | Control | Input | TTL, active low | Z80 Memory Request input. |
| 30 | /RAS | Control | Output | TTL, active low | DRAM Row Address Strobe. |
| 31 | READY | Control | Output | TTL | Wait-state generator output to Z80 Pin 24 (/WAIT) — stretches Z80 cycles so CPU and video never collide. |
| 32 | /INT | Control | Output | TTL, active low | 300 Hz Raster Interrupt output to Z80 Pin 16 (fires every 52 HSYNC scanlines). |
| 33 | /IORQ | Control | Input | TTL, active low | Z80 I/O Request input. |
| 34 | A15 | Address Bus | Input | TTL | Z80 Address bit 15 (with A14 selects Lower vs Upper ROM window). |
| 35 | A14 | Address Bus | Input | TTL | Z80 Address bit 14 (0 lowers Gate Array I/O decode during OUT (&7Fxx),A). |
| 36 | /ROMEN | Control | Input | TTL | External Expansion Port ROM disable input (/ROMDIS). |
| 37 | /RAMRD | Control | Output | TTL, active low | RAM Read enable. |
| 38 | /RESET | Control | Input | TTL, active low | System Reset input. |
| 39 | INKEN | Control | Output | TTL | Ink / Sync output control. |
| 40 | VSS | Ground | Power | 0 V | System ground (0 V). |
Common uses and repair diagnostics
The 40-pin Amstrad Gate Array (40007 in early CPC 464s; 40010 in late CPC 464s, CPC 664, and non-cost-reduced CPC 6128s — both 100% pin-compatible with each other!) works in tandem with the Motorola/Hitachi 6845 CRTC. Driven by a 16.000 MHz crystal, the Gate Array generates the 4.0 MHz Z80 CPU clock (PHI), the 1.0 MHz character clock (CCLK) for the 6845 CRTC, arbitrates zero-contention DRAM access via /READY wait states, controls Lower ($0000) and Upper ($C000) ROM banking, and converts video RAM bytes into Mode 0 (160x200, 16 colours), Mode 1 (320x200, 4 colours), and Mode 2 (640x200, 2 colours) across a 27-colour ternary (0 V / 2.5 V / 5 V) RGB palette!
Used in the Amstrad CPC 464, CPC 664, and CPC 6128 (non-cost-reduced boards). Notice how the Gate Array achieves 27 colours from only three RGB pins (Pins 5, 6, 8): each pin is a tri-state output that can drive 0 V (0% brightness), float Hi-Z into an external voltage divider (~50% brightness), or drive +5 V (100% brightness)!
- Scope Pin 4 (PHI) for 4.0 MHz and Pin 20 (CCLK) for 1.0 MHz. If 16 MHz is oscillating on Pins 1-2 but PHI or CCLK is dead, the 40007/40010 Gate Array has failed.
- Remember on the CPC 6128: IC119 (40010) is the 40-pin Gate Array, whereas IC118 (40008) is a 20-pin 128 KB RAM Banking PAL — do not mix up the part numbers!