Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | PHI0 | Clock / Timing | Input | TTL clock | Phase 0 clock input. Supplied by the TED chip, which generates the system clock in the C16/Plus-4. |
| 2 | RDY | Control | Input | TTL | Ready. Pulled low to stretch the current read cycle. |
| 3 | /IRQ | Control | Input | TTL, active low | Active low. Maskable interrupt request. There is NO /NMI pin on the 8501. |
| 4 | AEC | Control | Input | TTL | Address Enable Control. Low floats the address bus and R/W so the TED can drive them. On the 6510 this pin is /NMI; the whole pinout is shifted by one from pin 4 onwards. |
| 5 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. |
| 6 | A0 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 0. Tri-stated when AEC is low. |
| 7 | A1 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 1. |
| 8 | A2 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 2. |
| 9 | A3 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 3. |
| 10 | A4 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 4. |
| 11 | A5 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 5. |
| 12 | A6 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 6. |
| 13 | A7 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 7. |
| 14 | A8 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 8. |
| 15 | A9 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 9. |
| 16 | A10 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 10. |
| 17 | A11 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 11. |
| 18 | A12 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 12. |
| 19 | A13 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 13. |
| 20 | GND | Ground | Power | 0 V | Ground. Single ground pin. |
| 21 | A14 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 14. |
| 22 | A15 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 15, the most significant address line. |
| 23 | GATE IN | Control | Input | TTL | Gate input. Has no equivalent on the 6510; used in the C16/Plus-4 for TED-related bus gating. |
| 24 | P7 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 7. The port has SEVEN pins, not eight: P7, P6, then P4 (no P5). The missing P5 is the sharpest trap on this chip. |
| 25 | P6 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 6. |
| 26 | P4 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 4. Note the gap: there is no P5 pin. Wikipedia says the port was extended to 8 bits, but the CSG and Schepers pin tables agree on 7 bonded pins. |
| 27 | P3 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 3. |
| 28 | P2 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 2. |
| 29 | P1 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 1. |
| 30 | P0 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 0. |
| 31 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 7. The data bus DESCENDS: D7 here at pin 31 down to D0 at pin 38. |
| 32 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 6. |
| 33 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 5. |
| 34 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 4. |
| 35 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 3. |
| 36 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 2. |
| 37 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 1. |
| 38 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 0. |
| 39 | R/W | Control | Output | TTL, 0 V / 5 V | Read / Write. High during a read, low during a write. On the 6510 this pin is PHI2; the 8501 has no PHI2 output because the TED generates the clock. |
| 40 | /RES | Control | Input | TTL, active low | Active low. Reset. Held low on power-up to force the CPU to fetch the reset vector. |
Common uses and repair diagnostics
The MOS 8501 is the CPU of the Commodore 16, 116 and Plus/4: a 6502 core with a 7-bit I/O port and an AEC input, but no /NMI and no PHI2 output — the TED chip generates the system clock in these machines. It is NOT pin-compatible with the 6502 or the 6510; from pin 4 onwards the pinout is shifted by one relative to the 6510, and the two cannot be swapped. The 7501 is the HMOS-1 version; the 8501 is HMOS-2. The two are otherwise identical and interchangeable.
The 8501 is the CPU of the Commodore 16, 116 and Plus/4. It is a 6502 core with a 7-bit I/O port, but it is the sharpest trap in the 6502 family: the port has SEVEN pins, not eight, and the missing one is P5 — the sequence runs P7, P6, P4 on pins 24, 25, 26 with no P5 between them. It also has no /NMI (pin 4 is AEC instead) and no PHI2 output (pin 39 is R/W instead, because the TED generates the system clock). From pin 4 onwards the pinout is shifted by one relative to the 6510, so a 6510 will not work in an 8501 socket and vice versa.
These machines run hot and the 8501 is a very common failure. A heatsink is a worthwhile preventative fit on a working C16 or Plus/4, and a dead one usually has a cooked 8501 at the root of it.
- Scope pin 1 (PHI0) for a clean clock from the TED. No clock means the TED has failed, not the CPU.
- Check pin 5 (VCC) at 5 V and pin 20 (GND) at 0 V.
- Probe pin 4 (AEC); if it is stuck low the CPU never drives the bus. The fault is usually the TED, not the 8501.
- If the machine runs hot, check the 8501 temperature after a few minutes. These CPUs run hot and are a common failure; a heatsink is preventative.
- Remember there is no /NMI and no PHI2 output — do not expect them on pins 4 and 39 as on the 6510.