Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 7. The data bus descends D7 (pin 1) to D0 (pin 8). |
| 2 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 6. |
| 3 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 5. |
| 4 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 4. |
| 5 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 3. |
| 6 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 2. |
| 7 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 1. |
| 8 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 0. |
| 9 | CLK0 | Clock / Timing | Input | TTL clock | Counter 0 clock input. Counter 0 pins are CLK, OUT, GATE on pins 9, 10, 11. |
| 10 | OUT0 | Control | Output | TTL | Counter 0 output. On the IBM PC, counter 0 drives the system tick at 18.2 Hz. |
| 11 | GATE0 | Control | Input | TTL, active high | Counter 0 gate. High enables counting. A GATE left floating or stuck low stops that counter dead. |
| 12 | GND | Ground | Power | 0 V | Ground. Sits in the middle of the counter pins, between GATE0 (pin 11) and OUT1 (pin 13). |
| 13 | OUT1 | Control | Output | TTL | Counter 1 output. Counter 1 pins are OUT, GATE, CLK on pins 13, 14, 15 — a different order from counter 0. On the IBM PC, counter 1 drives DRAM refresh. |
| 14 | GATE1 | Control | Input | TTL, active high | Counter 1 gate. High enables counting. |
| 15 | CLK1 | Clock / Timing | Input | TTL clock | Counter 1 clock input. |
| 16 | GATE2 | Control | Input | TTL, active high | Counter 2 gate. High enables counting. Counter 2 pins are GATE, OUT, CLK on pins 16, 17, 18 — yet another order. |
| 17 | OUT2 | Control | Output | TTL | Counter 2 output. On the IBM PC, counter 2 drives the PC speaker tone. |
| 18 | CLK2 | Clock / Timing | Input | TTL clock | Counter 2 clock input. |
| 19 | A0 | Address Bus | Input | TTL | Address bit 0. A0 (pin 19) and A1 (pin 20) select one of four registers: the control word or one of the three counters. |
| 20 | A1 | Address Bus | Input | TTL | Address bit 1. Note A1 is on the HIGHER pin number (20) and A0 on 19 — they ascend, unlike the 8255 where A1 is lower. |
| 21 | /CS | Control | Input | TTL, active low | Active low. Chip select. Low enables the data bus for register access. |
| 22 | /RD | Control | Input | TTL, active low | Active low. Read strobe. Low reads the selected counter onto the data bus. |
| 23 | /WR | Control | Input | TTL, active low | Active low. Write strobe. Low writes the data bus to the selected counter or the control word. |
| 24 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The Intel 8253 PIT (Programmable Interval Timer) contains three independent 16-bit counters, each with six operating modes and its own clock, gate and output. The signature trap is that the three counters' pins appear in three DIFFERENT orders: counter 0 is CLK, OUT, GATE (pins 9, 10, 11); counter 1 is OUT, GATE, CLK (13, 14, 15); counter 2 is GATE, OUT, CLK (16, 17, 18). There is no pattern to memorise and no way to infer one counter's layout from another — give the reader the table and say so. The 8254 is pin compatible and a straight upgrade, adding the read-back command.
The Intel 8253 PIT contains three independent 16-bit counters, each with six operating modes and its own clock, gate and output. The signature trap is that the three counters' pins appear in three DIFFERENT orders: counter 0 is CLK, OUT, GATE (pins 9, 10, 11); counter 1 is OUT, GATE, CLK (13, 14, 15); counter 2 is GATE, OUT, CLK (16, 17, 18). There is no pattern to memorise and no way to infer one counter's layout from another — give the reader the table and say so. GND (pin 12) sits in the middle of the counter pins, between GATE0 (pin 11) and OUT1 (pin 13).
Counters can be loaded in binary or BCD, and read on the fly — but on the 8253 an on-the-fly read can catch the counter mid-update and return a torn value. The 8254 adds the read-back command that fixes this, and is otherwise pin compatible and a straight upgrade. Say that clearly, because it is the usual reason to prefer an 8254.
Used in the IBM PC and clones (counter 0 the system tick at 18.2 Hz, counter 1 DRAM refresh, counter 2 the PC speaker tone), the MSX, and a lot of arcade hardware. On a PC-compatible, a dead counter 1 historically meant memory corruption, which makes this chip far more critical than its size suggests. A GATE input left floating or stuck low stops that counter dead, so a single dead timer channel with a good clock usually means a gate problem on the board rather than a failed chip.
- Check for a clock on pins 9 (CLK0), 15 (CLK1) and 18 (CLK2) — those are the three counter clocks.
- Program a counter in mode 3 (square wave) and look for the divided output on its OUT pin (10, 13 or 17).
- A single dead timer channel with a good clock usually means a GATE problem on the board, not a failed chip. Check GATE0 (pin 11), GATE1 (pin 14) or GATE2 (pin 16).
- On a PC-compatible, a dead counter 1 (pin 13 OUT1) historically meant memory corruption from lost DRAM refresh.
- If on-the-fly reads return torn values, upgrade to the 8254 — it is pin compatible and adds the read-back command.