Pinout diagram
Summary specifications
Technology
NMOS (6567/6569) / HMOS (8562/8565)
VCC Supply
+5 V (pin 40)
VDD Supply
+12 V on pin 13 (6567/6569) or +5 V (8562/8565) — NOT interchangeable
VSS Supply
0 V (pin 20)
Address Bus
14-bit, multiplexed (A0-A6 on pins 24-30 carry A8-A13 on the second half-cycle)
Video Outputs
Composite colour (pin 14) and separate luma (pin 15)
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 6. The main data bus D0-D7 is on pins 1-7 and 39. |
| 2 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 5. |
| 3 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 4. |
| 4 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 3. |
| 5 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 2. |
| 6 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 1. |
| 7 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 0. |
| 8 | /IRQ | Control | Open-drain / open-collector | TTL, active low, open drain | Active low. Interrupt request, open-drain. Asserted during a raster interrupt or light-pen hit. |
| 9 | LP | Control | Input | TTL | Light Pen. A negative edge latches the current raster position into the light-pen registers. |
| 10 | /CS | Control | Input | TTL, active low | Active low. Chip select. Low enables the data bus for register access. |
| 11 | R/W | Control | Input | TTL | Read / Write. High reads a register, low writes one. |
| 12 | BA | Control | Output | TTL | Bus Available. Goes high when the VIC-II needs the bus (during badlines); the CPU must finish its cycle and wait. |
| 13 | VDD | Power | Power | +12 V (6567/6569) or +5 V (8562/8565) | Analogue supply. +12 V on the NMOS 6567/6569, +5 V on the HMOS 8562/8565. The two families are NOT interchangeable: fitting an 8565 where a 6569 belongs puts 12 V into a 5 V part. C64 boards 250407 and earlier are 12 V; 250425/250466/250469 are 5 V. |
| 14 | COLOR | Analog | Output | Analogue composite | Composite colour output. Carries the chroma signal to the RF modulator or video connector. |
| 15 | S/LUM | Analog | Output | Analogue composite | Separate luma output. The brightness signal; combined with COLOR for composite video. |
| 16 | AEC | Control | Output | TTL | Address Enable Control. Goes low to float the CPU bus so the VIC-II can drive the address lines and fetch its data. |
| 17 | PHI0 | Clock / Timing | Output | TTL clock | Phase 0 clock output. The 1 MHz CPU clock, derived from the VIC-II colour clock. The VIC-II generates the whole machine timing. |
| 18 | /RAS | Control | Output | TTL, active low | Active low. Row Address Strobe. Drives the DRAM row latch. |
| 19 | /CAS | Control | Output | TTL, active low | Active low. Column Address Strobe. Drives the DRAM column latch. |
| 20 | VSS | Ground | Power | 0 V | Ground. One of three supply pins: VDD (13), VSS (20), VCC (40). |
| 21 | PHCL | Clock / Timing | Input | TTL clock | Phi colour clock input. The high-frequency colour carrier clock from which the system clock is divided. |
| 22 | PHIN | Clock / Timing | Input | TTL clock | Phi input clock. Works with PHCL to clock the video timing. |
| 23 | A11 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 11. Carried separately — NOT multiplexed, unlike A0-A6 on pins 24-30. |
| 24 | A0 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 0. MULTIPLEXED: carries A0 on the first half-cycle and A8 on the second. Pins 24-30 are multiplexed this way. |
| 25 | A1 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 1. Multiplexed: carries A1 then A9. |
| 26 | A2 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 2. Multiplexed: carries A2 then A10. |
| 27 | A3 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 3. Multiplexed: carries A3 then A11. |
| 28 | A4 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 4. Multiplexed: carries A4 then A12. |
| 29 | A5 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 5. Multiplexed: carries A5 then A13. |
| 30 | A6 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 6. Multiplexed: carries A6 then a constant logic 1 (not A14) on the second half-cycle. |
| 31 | A7 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 7. Not multiplexed; carries A7 on both half-cycles. |
| 32 | A8 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 8. Not multiplexed; carries A8 on both half-cycles. |
| 33 | A9 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 9. Not multiplexed; carries A9 on both half-cycles. |
| 34 | A10 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 10. Not multiplexed; carries A10 on both half-cycles. |
| 35 | D11 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Colour RAM data bit 3. D8 to D11 (pins 35-38) are a SEPARATE 4-bit bus to the colour RAM, not part of the main data bus. |
| 36 | D10 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Colour RAM data bit 2. |
| 37 | D9 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Colour RAM data bit 1. |
| 38 | D8 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Colour RAM data bit 0. |
| 39 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 7, the most significant line of the main data bus. |
| 40 | VCC | Power | Power | +5 V | Logic supply. Decouple with 100 nF close to the pin. One of three supply pins: VDD (13), VSS (20), VCC (40). |
Common uses and repair diagnostics
The MOS VIC-II is the video chip at the heart of the Commodore 64. It generates the display, the 1 MHz system clock, and the /RAS and /CAS signals that drive the DRAM — so a dead VIC-II stops the CPU too, and no picture plus no sign of life does not rule it out. The headline trap is the supply: pin 13 is +12 V on the NMOS 6567/6569 but +5 V on the HMOS 8562/8565. The two families are NOT interchangeable without rewiring pin 13.
The VIC-II is the Commodore 64 video chip. It generates the display, the 1 MHz system clock (PHI0, pin 17) and the /RAS and /CAS signals that drive the DRAM, so a dead VIC-II stops the CPU too — no picture plus no sign of life does not rule it out. It takes the bus from the CPU using BA (pin 12) and AEC (pin 16) during badlines, and its multiplexed address bus (pins 24-30 carry A0-A6 then A8-A13) is why it can drive DRAM directly.
The supply trap is the headline: pin 13 is +12 V on the NMOS 6567/6569 but +5 V on the HMOS 8562/8565. Fitting a 6569 into a board wired for an 8565 gives no video; fitting an 8565 where a 6569 belongs puts 12 V into a 5 V part. C64 boards 250407 and earlier are 12 V; 250425, 250466 and 250469 are 5 V. The 6567 is NTSC, the 6569 is PAL-B; the 8562 and 8565 are the 5 V HMOS versions. The 6566 is a different, non-multiplexed variant and is NOT pin-compatible.
- Check pin 40 (VCC) at 5 V, pin 20 (VSS) at 0 V, and pin 13 (VDD) at the correct voltage for the board (12 V or 5 V). The wrong VDD kills the chip.
- No picture AND no sign of life: the VIC-II generates the CPU clock, so a dead VIC-II stops the whole machine. Probe pin 17 (PHI0) for a 1 MHz clock.
- Missing or wrong colours: probe the colour RAM bus (D8-D11, pins 35-38) and the colour output (pin 14).
- Garbled characters or vertical bars: often a failing VIC-II. Feel the chip — it runs extremely hot and is a common failure.
- Before replacing, confirm the board revision: 250407 and earlier want 12 V on pin 13; 250425/250466/250469 want 5 V. The wrong chip on the wrong board will fail immediately.