Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | /RAS | Control | Output | TTL, active low | Active low. Row Address Strobe. The VDP generates /RAS and /CAS itself to drive its dedicated DRAM directly. |
| 2 | /CAS | Control | Output | TTL, active low | Active low. Column Address Strobe. |
| 3 | AD7 | Address Bus | Output | TTL, 0 V / 5 V | VRAM address/write data bit 7. The AD bus descends: AD7 here down to AD0 on pin 10. OUTPUT only — the VDP drives the VRAM. Note: AD0 is the most significant bit on this bus (TI MSB-first convention). |
| 4 | AD6 | Address Bus | Output | TTL, 0 V / 5 V | VRAM address/write data bit 6. |
| 5 | AD5 | Address Bus | Output | TTL, 0 V / 5 V | VRAM address/write data bit 5. |
| 6 | AD4 | Address Bus | Output | TTL, 0 V / 5 V | VRAM address/write data bit 4. |
| 7 | AD3 | Address Bus | Output | TTL, 0 V / 5 V | VRAM address/write data bit 3. |
| 8 | AD2 | Address Bus | Output | TTL, 0 V / 5 V | VRAM address/write data bit 2. |
| 9 | AD1 | Address Bus | Output | TTL, 0 V / 5 V | VRAM address/write data bit 1. |
| 10 | AD0 | Address Bus | Output | TTL, 0 V / 5 V | VRAM address/write data bit 0. The MOST significant bit on this bus (TI MSB-first convention) — not the equivalent of "D0" anywhere else in this library. |
| 11 | R/W | Control | Output | TTL | Read / Write for the VRAM. Low writes. The internal slash is NOT an active-low marker — describe the two levels. (TI prints this with a bar over the W.) |
| 12 | VSS | Ground | Power | 0 V | Ground. VCC is pin 33 — neither at a corner. |
| 13 | MODE | Control | Input | TTL | Mode. Selects whether a CPU access targets the address register or the data register. |
| 14 | /CSW | Control | Input | TTL, active low | Active low. CPU Write Strobe. Two separate strobes rather than one R/W line on the CPU side. |
| 15 | /CSR | Control | Input | TTL, active low | Active low. CPU Read Strobe. The other half of the two-strobe CPU interface. |
| 16 | /INT | Control | Output | TTL, active low | Active low. Interrupt. Asserted to the host CPU on a vertical blank or other VDP event. |
| 17 | CD7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | CPU data bit 7. The CD bus descends: CD7 here down to CD0 on pin 24. Bidirectional — the CPU reads and writes through this bus. Note: CD0 is the most significant bit on this bus (TI MSB-first convention). |
| 18 | CD6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | CPU data bit 6. |
| 19 | CD5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | CPU data bit 5. |
| 20 | CD4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | CPU data bit 4. |
| 21 | CD3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | CPU data bit 3. |
| 22 | CD2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | CPU data bit 2. |
| 23 | CD1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | CPU data bit 1. |
| 24 | CD0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | CPU data bit 0. The MOST significant bit on this bus (TI MSB-first convention) — not the equivalent of "D0" anywhere else in this library. |
| 25 | RD7 | Data Bus | Input | TTL, 0 V / 5 V | VRAM read data bit 7. The RD bus descends: RD7 here down to RD0 on pin 32. INPUT only — a separate read path from VRAM. Note: RD0 is the most significant bit on this bus (TI MSB-first convention). |
| 26 | RD6 | Data Bus | Input | TTL, 0 V / 5 V | VRAM read data bit 6. |
| 27 | RD5 | Data Bus | Input | TTL, 0 V / 5 V | VRAM read data bit 5. |
| 28 | RD4 | Data Bus | Input | TTL, 0 V / 5 V | VRAM read data bit 4. |
| 29 | RD3 | Data Bus | Input | TTL, 0 V / 5 V | VRAM read data bit 3. |
| 30 | RD2 | Data Bus | Input | TTL, 0 V / 5 V | VRAM read data bit 2. |
| 31 | RD1 | Data Bus | Input | TTL, 0 V / 5 V | VRAM read data bit 1. |
| 32 | RD0 | Data Bus | Input | TTL, 0 V / 5 V | VRAM read data bit 0. The MOST significant bit on this bus (TI MSB-first convention). |
| 33 | VCC | Power | Power | +5 V | Positive supply. Single +5 V part. Decouple with 100 nF close to the pin. VSS is pin 12 — neither at a corner. |
| 34 | /RESET | Control | Input | TTL, active low | Active low. Reset. DUAL-FUNCTION and mildly hazardous: it is an active-low reset, but when driven above +9 V it becomes a sync input for external video. Do not treat it as a plain TTL reset pin without checking the board. |
| 35 | EXTVDP | Analog | Input | Analogue video | External VDP input. Accepts video from another VDP so two can be cascaded or overlaid. |
| 36 | COMVID | Analog | Output | Analogue composite | Composite video output. The combined colour and sync signal to the RF modulator or video connector. |
| 37 | GROMCLK | Clock / Timing | Output | TTL clock | GROM Clock output. At a twenty-fourth of the crystal frequency, for TI's GROM chips. |
| 38 | CPUCLK | Clock / Timing | Output | TTL clock | CPU Clock output. At a third of the crystal (~3.58 MHz from 10.7386 MHz), for the host CPU. If the VDP supplies the host CPU clock, a dead VDP stops the whole machine. |
| 39 | XTAL1 | Clock / Timing | Input | Crystal | Crystal input 1. A 10.7386 MHz crystal (three times the NTSC colour burst) connects across XTAL1 and XTAL2. Secondary references sometimes transpose XTAL1 and XTAL2; the crystal connects across both so it does not matter in practice. |
| 40 | XTAL2 | Clock / Timing | Output | Crystal | Crystal input 2. Drives the other side of the crystal. |
Common uses and repair diagnostics
The Texas Instruments TMS9918A is a Video Display Processor — it drives its own dedicated DRAM directly, generating /RAS and /CAS itself, and produces a composite colour video output. The headline, and the thing anyone wiring this chip from a modern pinout habit will get wrong, is that every bus on this chip is numbered backwards. TI inherited the TMS9900's MSB-first bit numbering, so on this part CD0, AD0 and RD0 are the MOST significant bits and CD7, AD7, RD7 are the least. "CD0" is not the equivalent of "D0" anywhere else in this library. Make this the headline — anyone wiring a TMS9918A from a modern pinout habit will get the bus mirrored.
The TMS9918A is the Video Display Processor behind the MSX and MSX2 (as the 9918A/9938), the ColecoVision, the TI-99/4A, the Sega SG-1000, the Memotech, the Sord M5 and the Tomy Tutor. It drives its own dedicated DRAM directly, generating /RAS (pin 1) and /CAS (pin 2) itself. In the TI-99/4A that memory is 4116s — see that page.
The headline, and the thing anyone wiring this chip from a modern pinout habit will get wrong, is that every bus on this chip is numbered backwards. TI inherited the TMS9900's MSB-first bit numbering, so CD0, AD0 and RD0 are the MOST significant bits and CD7, AD7, RD7 are the least. "CD0" is not the equivalent of "D0" anywhere else in this library. Two of the four sources state this explicitly. Make this the headline.
THREE separate 8-bit buses, using 24 of the 40 pins: CD0-CD7 (pins 24 down to 17) the bidirectional CPU data bus; AD0-AD7 (pins 10 down to 3) the VRAM address bus, which also carries write data to VRAM, output only; RD0-RD7 (pins 32 down to 25) the VRAM read data bus, input only. Separate read and write paths to VRAM is unusual and worth explaining: it is how the chip hits the bandwidth needed for full-colour sprites.
Pin 11 R/W controls the VRAM write; low writes. (Printed with a bar over the W in TI's documents — describe the two levels, do not call it active low.) MODE (13) selects whether a CPU access targets the address register or data. /CSW (14) is the CPU write strobe and /CSR (15) the read strobe — two separate strobes rather than one R/W line on the CPU side. Pin 34 is dual-function and mildly hazardous: it is an active-low reset, but when driven above +9 V it becomes a sync input for external video. Do not treat it as a plain TTL reset pin without checking the board. EXTVDP (35) accepts video from another VDP so two can be cascaded or overlaid.
Clock: a 10.7386 MHz crystal (three times the NTSC colour burst) across XTAL1 (39) and XTAL2 (40). The chip divides it down and offers CPUCLK (38) at a third of it (~3.58 MHz) for the host CPU, and GROMCLK (37) at a twenty-fourth for TI's GROM chips. Note that secondary references sometimes transpose XTAL1 and XTAL2; the crystal connects across both so it does not matter in practice. VCC is pin 33 and VSS is pin 12 — neither at a corner. Single +5 V part.
Variants: the TMS9928A replaces pins 38, 36 and 35 with component video outputs R-Y, Y and B-Y, so it has NO composite output and NO CPUCLK — it is therefore not a drop-in for a TMS9918A. The TMS9929A is the PAL version of the 9928A.
- Crystal activity on pins 39/40 first, then CPUCLK on pin 38. If the VDP supplies the host CPU clock, a dead VDP stops the whole machine.
- No picture with a good clock: check the VRAM on RD0-RD7 (pins 25-32) and the /RAS and /CAS strobes (pins 1, 2).
- Garbage or snow on screen with correct sync usually means failed VRAM rather than a failed VDP.
- Remember every bus is MSB-first: CD0, AD0, RD0 are the most significant bits. A bus wired to modern convention will be mirrored.
- Pin 34 (/RESET) is dual-function: above +9 V it becomes a sync input. Check the board before treating it as a plain reset.