Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | 1A | I/O | Input | TTL, 0 V / 5 V | Gate 1, input A. An unused input must be tied high, not left floating. |
| 2 | 1B | I/O | Input | TTL, 0 V / 5 V | Gate 1, input B. |
| 3 | 1Y | I/O | Output | TTL totem-pole | Gate 1 output. High only when both 1A and 1B are high. |
| 4 | 2A | I/O | Input | TTL, 0 V / 5 V | Gate 2, input A. |
| 5 | 2B | I/O | Input | TTL, 0 V / 5 V | Gate 2, input B. |
| 6 | 2Y | I/O | Output | TTL totem-pole | Gate 2 output. High only when both 2A and 2B are high. |
| 7 | GND | Ground | Power | 0 V | Ground return for all four gates. |
| 8 | 3Y | I/O | Output | TTL totem-pole | Gate 3 output. High only when both 3A and 3B are high. |
| 9 | 3A | I/O | Input | TTL, 0 V / 5 V | Gate 3, input A. |
| 10 | 3B | I/O | Input | TTL, 0 V / 5 V | Gate 3, input B. |
| 11 | 4Y | I/O | Output | TTL totem-pole | Gate 4 output. High only when both 4A and 4B are high. |
| 12 | 4A | I/O | Input | TTL, 0 V / 5 V | Gate 4, input A. |
| 13 | 4B | I/O | Input | TTL, 0 V / 5 V | Gate 4, input B. |
| 14 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. |
Common uses and repair diagnostics
The 74LS08 holds four independent 2-input AND gates in a 14-pin DIP, and unlike the 74LS02 it follows the standard 74LS00 pinout exactly: inputs first, output third, on each group, with outputs on pins 3, 6, 8 and 11. It is the part you reach for when a signal should only assert when two conditions are both true — an enable that must wait for both a chip-select and a read strobe, a gate that opens only when the address is in range and the cycle is valid.
The 74LS08 is the standard AND-gate glue on boards that need a signal to assert only when two conditions coincide. It gates read and write strobes with chip-selects, qualifies clock enables with address-decode outputs, and builds the simple address-range comparators that decide whether a memory cycle hits RAM, ROM or I/O. Because the AND is the natural partner of the NAND, a board that uses both will often pair a 74LS00 and a 74LS08 next to each other, and the two share the same pinout — a 74LS08 will fit a 74LS00 socket physically, but the logic function is different, so check the schematic before swapping. The 74HC08 and 74HCT08 are the CMOS equivalents and drop straight in.
- With power off, probe pin 14 (VCC) to pin 7 (GND) for a low-ohms supply rail; a dead short or open points to a decoupling capacitor or the chip itself.
- Power up and check pin 14 sits at 4.75 to 5.25 V. A sagging rail pulls the gate outputs out of spec and is often the real fault, not the gate.
- Drive both inputs of a gate high and measure the output: it must rise above 2.7 V. A stuck-low output suggests a failed totem-pole transistor.
- Tie one input of an unused gate to VCC through a 1 kR resistor and leave the other grounded; a floating LS input drifts high and makes the gate oscillate, coupling noise onto the rails.
- If several gates misbehave at once, suspect the supply decoupling first — a 74LS08 with no bypass capacitor can glitch the whole board when its outputs switch.