Pinout diagram
Used in Retro Machine Hubs
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Summary specifications
Technology
N-channel silicon-gate MOS
Operating Voltage
THREE rails: VBB -5 V (pin 2), VCC +5 V (pin 1), VDD +12 V (pin 27), VSS 0 V (pin 26)
Clock
3.0 MHz 4-phase 12 V non-overlapping clock (/PHI1, /PHI2, /PHI3, /PHI4)
Address Bus
15 word-address pins A0-A14 (64 KB byte space; A0 is MSB, A14 is LSB!)
Data Bus
16-bit bidirectional D0-D15 (D0 is MSB, D15 is LSB!)
Serial I/O Bus
CRU (Communications Register Unit) via CRUIN, CRUOUT, CRUCLK
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | VCC | Power | Power | +5 V | +5 V logic supply. |
| 2 | VBB | Power | Power | -5 V | -5 V substrate bias supply. If missing, the TMS9900 will not run and can overheat. |
| 3 | WAIT | Control | Output | TTL | Wait state indicator. High when READY is low and the CPU is waiting on slow GROM or multiplexed memory. |
| 4 | /LOAD | Control | Input | TTL, active low | Non-maskable Load interrupt input. |
| 5 | HOLDA | Control | Output | TTL | Hold Acknowledge output (DMA active). |
| 6 | /RESET | Control | Input | TTL, active low | System Reset input (active low for at least 3 clock cycles). |
| 7 | IAQ | Control | Output | TTL | Instruction Acquisition output (high during opcode fetch). |
| 8 | /PHI1 | Clock / Timing | Input | 12 V MOS clock | Phase 1 clock input (12 V swing from TIM9904). |
| 9 | /PHI2 | Clock / Timing | Input | 12 V MOS clock | Phase 2 clock input. |
| 10 | A14 (LSB) | Address Bus | Tri-state output | TTL | Word address bit 14 (LEAST significant word address bit = byte address bit 1!). |
| 11 | A13 | Address Bus | Tri-state output | TTL | Address bit 13. |
| 12 | A12 | Address Bus | Tri-state output | TTL | Address bit 12. |
| 13 | A11 | Address Bus | Tri-state output | TTL | Address bit 11. |
| 14 | A10 | Address Bus | Tri-state output | TTL | Address bit 10. |
| 15 | A9 | Address Bus | Tri-state output | TTL | Address bit 9. |
| 16 | A8 | Address Bus | Tri-state output | TTL | Address bit 8. |
| 17 | A7 | Address Bus | Tri-state output | TTL | Address bit 7. |
| 18 | A6 | Address Bus | Tri-state output | TTL | Address bit 6. |
| 19 | A5 | Address Bus | Tri-state output | TTL | Address bit 5. |
| 20 | A4 | Address Bus | Tri-state output | TTL | Address bit 4. |
| 21 | A3 | Address Bus | Tri-state output | TTL | Address bit 3. |
| 22 | A2 | Address Bus | Tri-state output | TTL | Address bit 2. |
| 23 | A1 | Address Bus | Tri-state output | TTL | Address bit 1. |
| 24 | DBIN | Control | Output | TTL | Data Bus In. High when the TMS9900 is reading data from memory. |
| 25 | /PHI3 | Clock / Timing | Input | 12 V MOS clock | Phase 3 clock input. |
| 26 | VSS | Ground | Power | 0 V | System ground (0 V). |
| 27 | VDD | Power | Power | +12 V | +12 V main drain supply. |
| 28 | /PHI4 | Clock / Timing | Input | 12 V MOS clock | Phase 4 clock input. |
| 29 | /WE | Control | Tri-state output | TTL, active low | Write Enable strobe (active low). |
| 30 | CRUOUT | I/O | Output | TTL | Communications Register Unit serial data output (feeds TMS9901 I/O chip). |
| 31 | CRUIN | I/O | Input | TTL | CRU serial data input (reads keyboard/joystick bits from TMS9901). |
| 32 | /INTREQ | Control | Input | TTL, active low | Interrupt Request input (from TMS9901). |
| 33 | IC3 | Control | Input | TTL | Interrupt Code bit 3 (LSB of 4-bit interrupt priority level). |
| 34 | IC2 | Control | Input | TTL | Interrupt Code bit 2. |
| 35 | IC1 | Control | Input | TTL | Interrupt Code bit 1. |
| 36 | IC0 | Control | Input | TTL | Interrupt Code bit 0 (MSB). |
| 37 | NC | No Connect | Not connected | NC | No internal connection. |
| 38 | NC | No Connect | Not connected | NC | No internal connection. |
| 39 | NC | No Connect | Not connected | NC | No internal connection. |
| 40 | NC | No Connect | Not connected | NC | No internal connection. |
| 41 | D0 (MSB) | Data Bus | Bidirectional | TTL | Data bus bit 0 — MOST Significant Bit (weight 32768 / $8000)! |
| 42 | D1 | Data Bus | Bidirectional | TTL | Data bus bit 1. |
| 43 | D2 | Data Bus | Bidirectional | TTL | Data bus bit 2. |
| 44 | D3 | Data Bus | Bidirectional | TTL | Data bus bit 3. |
| 45 | D4 | Data Bus | Bidirectional | TTL | Data bus bit 4. |
| 46 | D5 | Data Bus | Bidirectional | TTL | Data bus bit 5. |
| 47 | D6 | Data Bus | Bidirectional | TTL | Data bus bit 6. |
| 48 | D7 | Data Bus | Bidirectional | TTL | Data bus bit 7 (LSB of High Byte). |
| 49 | D8 | Data Bus | Bidirectional | TTL | Data bus bit 8 (MSB of Low Byte). |
| 50 | D9 | Data Bus | Bidirectional | TTL | Data bus bit 9. |
| 51 | D10 | Data Bus | Bidirectional | TTL | Data bus bit 10. |
| 52 | D11 | Data Bus | Bidirectional | TTL | Data bus bit 11. |
| 53 | D12 | Data Bus | Bidirectional | TTL | Data bus bit 12. |
| 54 | D13 | Data Bus | Bidirectional | TTL | Data bus bit 13. |
| 55 | D14 | Data Bus | Bidirectional | TTL | Data bus bit 14. |
| 56 | D15 (LSB) | Data Bus | Bidirectional | TTL | Data bus bit 15 — LEAST Significant Bit (weight 1 / $0001)! |
| 57 | NC | No Connect | Not connected | NC | No internal connection. |
| 58 | NC | No Connect | Not connected | NC | No internal connection. |
| 59 | A0 (MSB) | Address Bus | Tri-state output | TTL | Word address bit 0 — MOST Significant Bit ($8000)! |
| 60 | CRUCLK | I/O | Output | TTL | CRU output clock strobe (latches CRUOUT bit into TMS9901). |
| 61 | /MEMEN | Control | Tri-state output | TTL, active low | Memory Enable (active low during any memory bus access). |
| 62 | READY | Control | Input | TTL | Memory Ready input. Pulled low by slow GROMs or the 16-to-8-bit multiplexer; if stuck low, Pin 3 (WAIT) stays high forever. |
| 63 | /HOLD | Control | Input | TTL, active low | DMA Hold request input. |
| 64 | NC | No Connect | Not connected | NC | No internal connection. |
Common uses and repair diagnostics
Designed in 1976 as a single-chip implementation of the Texas Instruments 990 minicomputer CPU and used in the TI-99/4 and TI-99/4A, the 64-pin TMS9900 is unlike any 8-bit CPU on the bench. First, it has NO general-purpose registers (R0-R15) on the die: instead, a 16-bit Workspace Pointer (WP) points to a 32-byte block in 16-bit Scratchpad RAM ($8300-$83FF). Second, it requires THREE supply rails (VBB = -5 V on pin 2, VCC = +5 V on pin 1, VDD = +12 V on pin 27) AND four non-overlapping 12 V clock phases (/PHI1 to /PHI4 from the TIM9904). Third, TI numbered both buses in big-endian order: A0 (pin 49) and D0 (pin 41) are the MOST significant bits!
The TMS9900 powers the Texas Instruments TI-99/4 and TI-99/4A home computers as well as the TM990 industrial minicomputer boards. On the TI-99/4A, only the 8 KB Console ROM ($0000-$1FFF) and 256-byte Scratchpad SRAM ($8300-$83FF) sit directly on the 16-bit zero-wait-state D0-D15 bus; all other peripherals and expansion RAM are accessed through a wait-state generator and 16-to-8-bit bus multiplexer.
- Verify all THREE supply rails first: Pin 1 (+5 V), Pin 2 (-5 V) and Pin 27 (+12 V) relative to Pin 26 (GND). A missing -5 V or +12 V rail stops the CPU cold and leaves the TMS9919 sound chip screaming.
- Check Pin 62 (READY) and Pin 3 (WAIT): if a faulty System GROM or dirty cartridge holds READY low, WAIT stays high (+5 V) and the CPU halts permanently.
- Remember TI's reversed bit order when probing: A0 (Pin 59) and D0 (Pin 41) are the MSBs ($8000), while A14 (Pin 10) and D15 (Pin 56) are the LSBs!