Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | VSS | Ground | Power | 0 V | Ground. VCC is pin 20, NOT pin 40. Pin 40 is VSYNC. |
| 2 | /RESET | Control | Input | TTL, active low | Active low. Reset. Coded TOGETHER with LPSTB (pin 3) to select the operating mode: reset, normal or test. Holding /RESET low stops the CRTC and clears the internal counters. |
| 3 | LPSTB | Control | Input | TTL, rising edge | Light Pen Strobe. Latches the current refresh address into the light pen register on a LOW-TO-HIGH transition — rising-edge triggered, so no leading slash. Coded together with /RESET (pin 2) to select the operating mode. |
| 4 | MA0 | Address Bus | Output | TTL, 0 V / 5 V | Memory address bit 0. The 14-bit refresh/screen memory address bus ASCENDS up pins 4 to 17: MA0 here, MA13 on pin 17. |
| 5 | MA1 | Address Bus | Output | TTL, 0 V / 5 V | Memory address bit 1. |
| 6 | MA2 | Address Bus | Output | TTL, 0 V / 5 V | Memory address bit 2. |
| 7 | MA3 | Address Bus | Output | TTL, 0 V / 5 V | Memory address bit 3. |
| 8 | MA4 | Address Bus | Output | TTL, 0 V / 5 V | Memory address bit 4. |
| 9 | MA5 | Address Bus | Output | TTL, 0 V / 5 V | Memory address bit 5. |
| 10 | MA6 | Address Bus | Output | TTL, 0 V / 5 V | Memory address bit 6. |
| 11 | MA7 | Address Bus | Output | TTL, 0 V / 5 V | Memory address bit 7. |
| 12 | MA8 | Address Bus | Output | TTL, 0 V / 5 V | Memory address bit 8. |
| 13 | MA9 | Address Bus | Output | TTL, 0 V / 5 V | Memory address bit 9. |
| 14 | MA10 | Address Bus | Output | TTL, 0 V / 5 V | Memory address bit 10. |
| 15 | MA11 | Address Bus | Output | TTL, 0 V / 5 V | Memory address bit 11. |
| 16 | MA12 | Address Bus | Output | TTL, 0 V / 5 V | Memory address bit 12. |
| 17 | MA13 | Address Bus | Output | TTL, 0 V / 5 V | Memory address bit 13, the most significant line of the refresh address bus. |
| 18 | DE | Control | Output | TTL | Display Enable. High while pixels are being displayed. Gate the video output with this to get proper blanking. |
| 19 | CURSOR | Control | Output | TTL | Cursor. Goes high when the refresh address matches the cursor register, marking the cursor position on screen. |
| 20 | VCC | Power | Power | +5 V | Positive supply. Single +5 V part. Decouple with 100 nF close to the pin. This is pin 20, not pin 40. |
| 21 | CLK | Clock / Timing | Input | TTL clock | Character clock. Derived from an external dot counter, it drives all the video timing. Feed the wrong clock here and the display timing is wrong while register writes still work. |
| 22 | R/W | Control | Input | TTL | Read / Write. High reads a register, low writes one. The internal slash is NOT an active-low marker. |
| 23 | E | Clock / Timing | Input | TTL clock | Enable clock. The 6800 bus enable clock for CPU register access only. Do not confuse with CLK (pin 21) — E is for register access, CLK is for video timing. |
| 24 | RS | Address Bus | Input | TTL | Register Select. Only ONE register-select line. The CRTC uses the classic address-register-then-data pair: write the register number to the address register, then the value to the data register. That is why 19 internal registers hide behind one select pin, and why you cannot read most of them back. |
| 25 | /CS | Control | Input | TTL, active low | Active low. Chip select. Low enables the data bus for register access. |
| 26 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 7. |
| 27 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 6. |
| 28 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 5. |
| 29 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 4. |
| 30 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 3. |
| 31 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 2. |
| 32 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 1. |
| 33 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 0. |
| 34 | RA4 | Address Bus | Output | TTL, 0 V / 5 V | Raster address bit 4. The 5-bit raster/row address bus DESCENDS: RA4 here on pin 34, RA0 on pin 38. Drives the character generator ROM row address. Getting this reversed gives a display with the scan lines of each character row in the wrong order — looks like a dead character ROM but is not. |
| 35 | RA3 | Address Bus | Output | TTL, 0 V / 5 V | Raster address bit 3. |
| 36 | RA2 | Address Bus | Output | TTL, 0 V / 5 V | Raster address bit 2. |
| 37 | RA1 | Address Bus | Output | TTL, 0 V / 5 V | Raster address bit 1. |
| 38 | RA0 | Address Bus | Output | TTL, 0 V / 5 V | Raster address bit 0. The least significant line of the raster address, on pin 38 — the opposite end from MA0 on pin 4. |
| 39 | HSYNC | Control | Output | TTL | Horizontal Sync. The horizontal synchronisation pulse for the display. |
| 40 | VSYNC | Control | Output | TTL | Vertical Sync. The vertical synchronisation pulse for the display. This is pin 40, not VCC. |
Common uses and repair diagnostics
The Motorola MC6845 is a CRT controller (CRTC) — it generates the video timing, the refresh address for the screen memory and the raster address for the character generator. The headline is the two separate address buses running in opposite directions: MA0-MA13 (the 14-bit refresh/screen memory address) ASCENDS up pins 4 to 17, while RA0-RA4 (the 5-bit raster/row address that drives the character generator ROM) DESCENDS — RA0 is on pin 38 and RA4 on pin 34. Getting the row address reversed gives a display with the scan lines of each character row in the wrong order, which looks like a dead character ROM but is not. Same 6800-family power trap: VSS pin 1, VCC pin 20. Pin 40 is VSYNC.
The MC6845 is the CRT controller behind the Amstrad CPC, the BBC Micro, the Commodore PET 80-column models (as the 6545), the original IBM MDA and CGA cards, and many terminals. It generates the video timing, the refresh address for the screen memory and the raster address for the character generator.
The headline is the two separate address buses running in OPPOSITE directions. MA0-MA13 (the 14-bit refresh/screen memory address) ASCENDS up pins 4 to 17. RA0-RA4 (the 5-bit raster/row address that drives the character generator ROM) DESCENDS — RA0 is on pin 38 and RA4 on pin 34. Getting the row address reversed gives a display with the scan lines of each character row in the wrong order, which looks like a dead character ROM but is not.
Two clock inputs with completely different jobs: CLK (pin 21) is the CHARACTER clock, derived from an external dot counter, and it drives all the video timing. E (pin 23) is the 6800 bus enable clock for CPU register access only. Feed the wrong one and the display timing is wrong while register writes still work. Only ONE register-select line, RS (pin 24). The CRTC uses the classic address-register-then-data pair: write the register number to the address register, then the value to the data register. That is why 19 internal registers hide behind one select pin, and why you cannot read most of them back.
/RESET (pin 2) and LPSTB (pin 3) are encoded TOGETHER to select the operating mode (reset, normal or test). LPSTB itself latches the current refresh address into the light pen register on a LOW-TO-HIGH transition — it is rising-edge triggered, so no leading slash. DE (pin 18, Display Enable) is high while pixels are being displayed; it is the signal you gate the video output with to get proper blanking. CURSOR (pin 19) goes high when the refresh address matches the cursor register.
Single +5 V part. Pin compatible with the MC6835; the Hitachi HD6845 and UMC UM6845 are the usual substitutes, though the CPC's "6845 type" differences (UM6845R vs HD6845S vs AMS 40489) change some register edge-case behaviour and are the reason some demos only run on certain machines.
- No HSYNC on pin 39 or VSYNC on pin 40 means the CRTC is not generating timing. Check CLK on pin 21 first — without a character clock there is nothing to divide.
- A monitor that shows a rolling or out-of-range picture usually means the CRTC registers were never initialised, which is a CPU or ROM problem rather than a CRTC fault.
- If the scan lines of each character row are in the wrong order, check the RA0-RA4 wiring (pins 34-38). The raster address bus descends — RA0 on pin 38, RA4 on pin 34.
- Do not confuse CLK (pin 21, video timing) with E (pin 23, register access). Feeding the wrong clock gives wrong display timing while register writes still work.
- Check pin 1 (VSS) at 0 V and pin 20 (VCC) at 5 V. Pin 40 is VSYNC, not VCC.