Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | A6 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 6. The address bus runs in three different directions: A6, A5, A4, A3 descend on pins 1-4; A0, A1, A2 ascend on pins 5-7; A7, A8, A9 appear on pins 17, 16, 15. No pattern to remember. |
| 2 | A5 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 5. |
| 3 | A4 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 4. |
| 4 | A3 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 3. |
| 5 | A0 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 0. The direction changes here: A0, A1, A2 ascend on pins 5-7. |
| 6 | A1 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 1. |
| 7 | A2 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 2. |
| 8 | /CS | Control | Input | TTL, active low | Active low. Chip Select. High deselects the chip and floats the DQ pins. /WE is ignored while deselected, so the DQ pins can be OR-tied straight onto a bus. |
| 9 | GND | Ground | Power | 0 V | Ground. VCC is pin 18 — diagonally opposite, the standard arrangement for an 18-pin part. |
| 10 | /WE | Control | Input | TTL, active low | Active low. Write Enable. Low writes the data on DQ1-DQ4 into the selected address. Ignored while /CS is high. |
| 11 | DQ4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bit 4. The data pins descend: DQ4, DQ3, DQ2, DQ1 on pins 11-14. Numbered from ONE — there is no DQ0. Some references print them as D1-D4 or DQ0-DQ3. |
| 12 | DQ3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bit 3. |
| 13 | DQ2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bit 2. |
| 14 | DQ1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bit 1. |
| 15 | A9 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 9. The top of the address bus: A7 (17), A8 (16), A9 (15) — descending as the pin number rises. |
| 16 | A8 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 8. |
| 17 | A7 | Address Bus | Input | TTL, 0 V / 5 V | Address bit 7. |
| 18 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. The 2114L is the low-power version and a direct substitute. |
Common uses and repair diagnostics
The 2114 is a 1024-word x 4-bit static RAM in an 18-pin DIP. Two things make this page worth reading before you wire one. First, the data pins are numbered from ONE, not zero: DQ1, DQ2, DQ3 and DQ4 — there is no DQ0. People assume D0-D3 and mis-wire the nibble. Second, the address pins run in three different directions: A6, A5, A4, A3 descend on pins 1-4; then A0, A1, A2 ascend on pins 5-7; then A7, A8, A9 appear on pins 17, 16, 15 — descending as the pin number rises. There is no pattern to remember; give the reader the table.
The 2114 is a 1024-word x 4-bit static RAM. Two chips side by side make a byte-wide 1K store — that is exactly how they are used, in pairs. A single failed 2114 corrupts one nibble of every byte in its bank, which shows up as consistently wrong characters or colours rather than a dead machine — a very recognisable symptom. Used in arcade boards by the dozen, the ZX81's 1K, Apple II peripheral cards, the TRS-80, early terminals, and the Commodore 1541's work RAM.
Two things make this chip easy to wire wrong. The data pins are numbered from ONE, not zero: DQ1, DQ2, DQ3 and DQ4 — there is no DQ0. People assume D0-D3 and mis-wire the nibble. Some references do print them as D1-D4 or DQ0-DQ3. The address pins run in three different directions: A6, A5, A4, A3 descend on pins 1-4; then A0, A1, A2 ascend on pins 5-7; then A7, A8, A9 appear on pins 17, 16, 15 — descending as the pin number rises. There is no pattern to remember. The data pins also descend: DQ4, DQ3, DQ2, DQ1 on pins 11-14.
Fully static: no clocks, no refresh, single +5 V. /CS (8) high deselects the chip and floats the DQ pins, and /WE is ignored while deselected, so the DQ pins can be OR-tied straight onto a bus. VCC is pin 18, GND is pin 9 — the standard arrangement for an 18-pin part, diagonally opposite. The 2114L is the low-power version and a direct substitute.
- With the chip selected, walk a pattern through each address and read it back. A bit that is always high or always low across every address is a failed DQ line.
- A fault that only appears in part of the range points at an address pin or its track, not the chip itself.
- Because they are used in pairs, swap the pair rather than guessing which half is bad, or compare the two chips' DQ activity on a scope.
- Remember the data pins are DQ1-DQ4, not DQ0-DQ3. A mis-wired nibble is the classic 2114 error.
- A single failed 2114 corrupts one nibble of every byte — consistently wrong characters or colours, not a dead machine.