Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | VSS | Ground | Power | 0 V | Ground. |
| 2 | /NMI | Control | Input | TTL, active low | Active low. Non-Maskable Interrupt. Stacks the entire register set and vectors to the NMI handler. The highest-priority interrupt. |
| 3 | /IRQ | Control | Input | TTL, active low | Active low. Interrupt Request. Maskable via the I bit in the condition code register. Stacks the entire register set. |
| 4 | /FIRQ | Control | Input | TTL, active low | Active low. Fast Interrupt Request. Stacks only the PC and CC (not the accumulators or index registers), which is why it is "fast". Maskable via the F bit. |
| 5 | BS | Control | Output | TTL | Bus Status. Together with BA (pin 6) encodes the processor state: normal, interrupt acknowledge, sync acknowledge or halt/bus-grant. A useful two-pin diagnostic. |
| 6 | BA | Control | Output | TTL | Bus Available. Together with BS (pin 5) encodes the processor state. High means the address and data buses are floated and the CPU is off the bus. |
| 7 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. |
| 8 | A0 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 0. The address bus is a clean contiguous run: A0-A15 straight up pins 8-23. Far friendlier to probe than the 8080 or the Z80. |
| 9 | A1 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 1. |
| 10 | A2 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 2. |
| 11 | A3 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 3. |
| 12 | A4 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 4. |
| 13 | A5 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 5. |
| 14 | A6 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 6. |
| 15 | A7 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 7. |
| 16 | A8 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 8. |
| 17 | A9 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 9. |
| 18 | A10 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 10. |
| 19 | A11 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 11. |
| 20 | A12 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 12. |
| 21 | A13 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 13. |
| 22 | A14 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 14. |
| 23 | A15 | Address Bus | Output | TTL, 0 V / 5 V | Address bit 15, the most significant address line. |
| 24 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 7. The data bus is a clean contiguous run: D7 down to D0 on pins 24-31. |
| 25 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 6. |
| 26 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 5. |
| 27 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 4. |
| 28 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 3. |
| 29 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 2. |
| 30 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 1. |
| 31 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 0. |
| 32 | R/W | Control | Output | TTL | Read / Write. High reads, low writes. Note the internal slash is NOT an active-low marker. |
| 33 | /DMA-BREQ | Control | Input | TTL, active low | Active low. DMA Bus Request. Low tri-states the address and data buses for an external DMA controller. On the 6809E this pin is BUSY instead. |
| 34 | E | Clock / Timing | Output | TTL clock | Phase E clock OUTPUT. The bus enable clock, at a quarter of the crystal frequency. On the 6809E this is an INPUT. People measuring E and expecting the crystal frequency get confused — a 4 MHz crystal gives 1 MHz here. |
| 35 | Q | Clock / Timing | Output | TTL clock | Phase Q clock OUTPUT. Leads E by 90 degrees. On the 6809E this is an INPUT and must be supplied externally with Q leading E. |
| 36 | /MRDY | Control | Input | TTL, active low | Active low. Memory Ready. Low stretches the E clock for slow memory. On the 6809E this pin is AVMA instead. |
| 37 | /RESET | Control | Input | TTL, active low | Active low. Reset. Held low for at least one full E cycle to reset the CPU and vector to the restart handler. |
| 38 | EXTAL | Clock / Timing | Input | Crystal | External crystal input. Connects to one side of the crystal; the other side goes to XTAL (pin 39). On the 6809E this pin is LIC (Last Instruction Cycle) instead. |
| 39 | XTAL | Clock / Timing | Output | Crystal | Crystal output. Drives the other side of the crystal. On the 6809E this pin is TSC (Three-State Control) instead. |
| 40 | /HALT | Control | Input | TTL, active low | Active low. Halt. Low stops the CPU and floats the buses. A /HALT stuck low holds the CPU off the bus and looks identical to a dead CPU — check this pin before condemning the chip. |
Common uses and repair diagnostics
The Motorola MC6809 is widely regarded as the most capable 8-bit microprocessor of its generation. It adds position-independent code, a hardware multiply instruction (MUL), and a rich addressing mode set to the 6800 architecture. The headline on this page is the distinction between the MC6809 and the MC6809E: on this part E (pin 34) and Q (pin 35) are clock OUTPUTS, generated internally from the crystal on EXTAL/XTAL. On the MC6809E they are INPUTS and must be supplied externally, with Q leading E. That single difference means the two are NOT interchangeable. The 6809E also replaces pin 33 /DMA-BREQ with BUSY, pin 36 /MRDY with AVMA, pin 38 EXTAL with LIC and pin 39 XTAL with TSC — four pins differ in total. The Dragon 32/64 and Tandy CoCo 1/2 use the 6809; the CoCo 3 uses the 6809E.
The MC6809 is the most capable 8-bit CPU of its generation. Position-independent code and a hardware multiply (MUL) put it ahead of the 6502 and Z80 in raw capability, and its clean contiguous buses — A0-A15 straight up pins 8-23, D7 down to D0 on 24-31 — make it far friendlier to probe than the 8080 or the Z80. The Dragon 32/64 and Tandy CoCo 1/2 use the 6809; the CoCo 3 uses the 6809E.
The headline is the 6809 vs 6809E distinction. On this part E (pin 34) and Q (pin 35) are clock OUTPUTS, generated internally from the crystal on EXTAL/XTAL. On the 6809E they are INPUTS and must be supplied externally, with Q leading E. That single difference means the two are NOT interchangeable. The 6809E also replaces pin 33 /DMA-BREQ with BUSY, pin 36 /MRDY with AVMA, pin 38 EXTAL with LIC and pin 39 XTAL with TSC — four pins differ in total. Internally the clock is divided by four: a 4 MHz crystal on EXTAL/XTAL gives a 1 MHz E clock, which confuses people measuring E and expecting the crystal frequency.
Three interrupts with different costs: /NMI and /IRQ stack the entire register set, /FIRQ (pin 4) stacks only PC and CC, which is why it is "fast". BA (pin 6) and BS (pin 5) together encode the processor state — normal, interrupt acknowledge, sync acknowledge or halt/bus-grant — and make a useful two-pin diagnostic.
- Check the crystal running on pin 38/39 first, then E on pin 34 at a quarter of the crystal frequency.
- /HALT (pin 40) stuck low holds the CPU off the bus and looks identical to a dead CPU. Probe it before condemning the chip.
- BA (pin 6) and BS (pin 5) together encode the processor state — check both to see whether the CPU is in normal, interrupt-acknowledge, sync or halt mode.
- If the machine uses a 6809E, do not swap in a 6809: E and Q are inputs on the 6809E and outputs on the 6809. Four pins differ in total.
- A /FIRQ or /IRQ stuck low holds the CPU in a tight interrupt loop. Lift the pin to isolate the fault.