Pinout diagram
Summary specifications
Full pin reference
| Pin | Name | Group | Direction | Levels | Description |
|---|---|---|---|---|---|
| 1 | PHI0 | Clock / Timing | Input | TTL clock | Phase 0 clock input. The system clock derived from the VIC-II; all bus timing is referenced to it. |
| 2 | RDY | Control | Input | TTL | Ready. Pulled low to stretch the current read cycle; the CPU waits until it returns high. |
| 3 | /IRQ | Control | Input | TTL, active low | Active low. Maskable interrupt request. |
| 4 | /NMI | Control | Input | TTL, active low | Active low. Non-maskable interrupt. Always serviced; the CPU fetches the NMI vector. |
| 5 | AEC | Control | Input | TTL | Address Enable Control. Low floats the address bus and R/W so the VIC-II can drive them. If AEC is stuck low the CPU never drives the bus and the machine looks dead. |
| 6 | VCC | Power | Power | +5 V | Positive supply. Decouple with 100 nF close to the pin. |
| 7 | A0 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 0. Tri-stated when AEC is low. |
| 8 | A1 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 1. |
| 9 | A2 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 2. |
| 10 | A3 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 3. |
| 11 | A4 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 4. |
| 12 | A5 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 5. |
| 13 | A6 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 6. |
| 14 | A7 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 7. |
| 15 | A8 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 8. |
| 16 | A9 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 9. |
| 17 | A10 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 10. |
| 18 | A11 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 11. |
| 19 | A12 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 12. |
| 20 | A13 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 13. |
| 21 | GND | Ground | Power | 0 V | Ground. Single ground pin, unlike the 6502 which has two. |
| 22 | A14 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 14. |
| 23 | A15 | Address Bus | Output | TTL, 0 V / 5 V | Address bus bit 15, the most significant address line. |
| 24 | P5 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 5. In the C64: cassette motor control. The port DESCENDS: P5 here at pin 24 down to P0 at pin 29. |
| 25 | P4 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 4. In the C64: cassette switch sense. |
| 26 | P3 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 3. In the C64: cassette data out. |
| 27 | P2 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 2. In the C64: /CHAREN — selects character ROM vs I/O. |
| 28 | P1 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 1. In the C64: /HIRAM — enables the upper 8 KB ROM bank. |
| 29 | P0 | I/O | Bidirectional | TTL, 0 V / 5 V | I/O port bit 0. In the C64: /LORAM — enables the lower 8 KB ROM bank. |
| 30 | D7 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 7. The data bus DESCENDS: D7 here at pin 30 down to D0 at pin 37. |
| 31 | D6 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 6. |
| 32 | D5 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 5. |
| 33 | D4 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 4. |
| 34 | D3 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 3. |
| 35 | D2 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 2. |
| 36 | D1 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 1. |
| 37 | D0 | Data Bus | Bidirectional | TTL, 0 V / 5 V | Data bus bit 0. |
| 38 | R/W | Control | Output | TTL, 0 V / 5 V | Read / Write. High during a read, low during a write. Tri-stated when AEC is low. |
| 39 | PHI2 | Clock / Timing | Output | TTL clock | Phase 2 clock output. The main system clock; used to time all bus access. |
| 40 | /RES | Control | Input | TTL, active low | Active low. Reset. Held low on power-up to force the CPU to fetch the reset vector. |
Common uses and repair diagnostics
The MOS 6510 is the CPU at the heart of the Commodore 64: a 6502 core with a 6-bit on-chip I/O port (P0 to P5) and an AEC input that lets the VIC-II steal the bus. It is NOT a pin-compatible 6502 — the pin assignments shift to make room for the port and AEC, so the two cannot be swapped. The 8500 is the HMOS-2 shrink of the 6510 and is pin-identical, a direct drop-in replacement.
The 6510 is the Commodore 64 CPU. Its 6-bit I/O port controls the memory bank switching that lets the C64 share its 64 KB between ROM, RAM and I/O: P0 (/LORAM) and P1 (/HIRAM) gate the BASIC and KERNAL ROMs, P2 (/CHAREN) selects the character ROM, and P3 to P5 drive the Datasette. A C64 that will not load from tape but is otherwise fine often has a failed port bit, not a failed Datasette.
The AEC pin (5) is the bus-acknowledge from the VIC-II: when AEC goes low the 6510 floats its address bus and R/W line so the video chip can fetch its own data. If AEC is stuck low the CPU never drives the bus and the machine looks dead. The 8500 is the HMOS-2 shrink of the 6510 and is pin-identical — a direct swap. The 6510 is NOT pin-compatible with the 6502; the pin assignments differ throughout.
- Scope pin 1 (PHI0) for a clean 1 MHz clock from the VIC-II. No clock means the VIC-II has failed, not the CPU.
- Check pin 6 (VCC) at 5 V and pin 21 (GND) at 0 V. The 6510 has a single ground pin, unlike the 6502.
- Probe pin 5 (AEC); if it is stuck low the CPU never drives the bus and the machine looks dead. The fault is usually the VIC-II, not the 6510.
- Read the I/O port register at $00/$01: a port bit stuck high or low that will not follow its data direction register points at a failed 6510.
- A C64 that boots but will not load from tape often has a failed P3, P4 or P5 bit, not a failed Datasette.